CHANGELOG.md



Changelog
All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog
and this project adheres to Semantic Versioning.

[Unreleased]

Added

Changed

Fix non-setable MEIE bit in MIE CSR
Bump fpnew to v0.6.2


4.2.0 - 2019-06-04

Added

Check execute PMA on instruction frontend
Add support for non-contiguous cacheable regions to the PMA checks
Provision exponential backoff for AMO SC in L1 D$ miss handler


Changed

Several small fixes to get the code running on VCS
Fix compressed instruction decoding in tracer
Fix privilege bug in performance counters. The counters have always been accessible in user mode.
Fix RISC-V PK simulation bug caused due to insufficient time to init the a0 and a1 registers via the bootrom
Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
Fix potentially long timing path in axi_lite_interface

Fix VCS elab warning in load_store_unit

Replace PLIC with implementation from lowRISC
Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
Bump fpnew to v0.5.5

Bump axi to v0.7.0

Bump common_cells to v1.13.1

Bump riscv-dbg to v0.1

Improve FPU pipelining and timing around scoreboard
Reworked the axilite to PLIC shim for OpenPiton+Ariane
Remove in and out aliases for AXI interfaces
Fix small issues with DC synthesis
Fix wrong dirtying of sd flag in mstatus

Synthesis fix for Vivado 2018.3

Clean-up instruction front-end, small IPC improvement
Move to Verilator 4.014


4.1.2

Update FPU headers (license)


4.1.1

Changed

Hotfix: add missing defines for OpenPiton cache system.


4.1.0

Added

Official support for floating point unit
Added AXI-64bit adapter for write-through cache system
Added AXI atomic ops and exclusive access support to write-through cache system
Provision riscv-isa-sim tandem simulation
Support for preloading