verifier: add a signal to lock I$ requests

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/verifier.sv

@@ -20,11 +20,18 @@ module verifier #(
 
   // CO
   input                             ariane_pkg::scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
-  input logic [NR_COMMIT_PORTS-1:0] commit_ack_i
+  input logic [NR_COMMIT_PORTS-1:0] commit_ack_i,
+
+  output logic                      should_lock_icache_o
 );
 
   localparam int unsigned           BITS_ENTRIES = $clog2(NR_ENTRIES);
 
+  // Bus accesses (I$ misses and memory instructions in the pipeline)
+  logic                             has_mem_access;
+  assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i;
+  assign should_lock_icache_o = has_mem_access & icache_miss_i;
+
   // CO
   logic [NR_COMMIT_PORTS-1:0][BITS_ENTRIES-1:0]          commit_id_n, commit_id_q;
   logic [NR_COMMIT_PORTS-1:0]       commit_correct;