Skip to content
Snippets Groups Projects
Commit 0e066983 authored by Nils Wistoff's avatar Nils Wistoff Committed by Florian Zaruba
Browse files

tb_read/writeport: add set and constant seq modes

parent 2b760a26
No related branches found
No related tags found
No related merge requests found
......@@ -36,7 +36,7 @@ package tb_pkg;
parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation...
// tb_readport sequences
typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ } seq_t;
typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ, SET_SEQ, CONST_SEQ } seq_t;
///////////////////////////////////////////////////////////////////////////////
// progress
......
......@@ -218,6 +218,33 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #(
dut_req_port_o.kill_req = '0;
endtask : genSeqRead
// Generate a sequence of reads to the same set (constant index)
task automatic genSetSeqRead();
automatic logic [63:0] val, rnd;
paddr = CachedAddrBeg + 2 ** DCACHE_INDEX_WIDTH;
dut_req_port_o.data_req = '0;
dut_req_port_o.data_size = '0;
dut_req_port_o.kill_req = '0;
val = CachedAddrBeg + 2 ** DCACHE_INDEX_WIDTH;
while(~seq_end_req) begin
void'(randomize(rnd) with {rnd > 0; rnd <= 100;});
if(rnd < req_rate_i) begin
dut_req_port_o.data_req = 1'b1;
dut_req_port_o.data_size = 2'b11;
paddr = val;
// generate linear read
`APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt)
// increment by set size
val = (val + 2 ** DCACHE_INDEX_WIDTH) % (MemWords<<3);
end
`APPL_WAIT_CYC(clk_i,1)
dut_req_port_o.data_req = '0;
end
dut_req_port_o.data_req = '0;
dut_req_port_o.data_size = '0;
dut_req_port_o.kill_req = '0;
endtask : genSetSeqRead
task automatic genWrapSeq();
automatic logic [63:0] val;
paddr = CachedAddrBeg;
......@@ -278,6 +305,10 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #(
$display("%s> start linear sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i);
genSeqRead();
end
SET_SEQ: begin
$display("%s> start set sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i);
genSetSeqRead();
end
WRAP_SEQ: begin
$display("%s> start wrapping sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i);
genWrapSeq();
......@@ -288,6 +319,9 @@ program tb_readport import tb_pkg::*; import ariane_pkg::*; #(
BURST_SEQ: begin
$fatal(1, "Burst sequence not implemented for read port agent");
end
CONST_SEQ: begin
$fatal(1, "Constant sequence not implemented for read port agent.");
end
endcase // seq_type_i
seq_end_ack = 1'b1;
$display("%s> stop sequence", PortName);
......
......@@ -149,6 +149,30 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #(
dut_req_port_o.data_wdata = 'x;
endtask : genSeqWrite
// Repeadedly write to the same address
task automatic genConstWrite();
automatic logic [63:0] val;
paddr = CachedAddrBeg;
dut_req_port_o.data_req = '0;
dut_req_port_o.data_size = '0;
dut_req_port_o.data_be = '0;
dut_req_port_o.data_wdata = 'x;
repeat(seq_num_vect_i) begin
void'(randomize(val));
dut_req_port_o.data_req = 1'b1;
dut_req_port_o.data_size = 2'b11;
dut_req_port_o.data_be = '1;
dut_req_port_o.data_wdata = val;
`APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt)
`APPL_WAIT_CYC(clk_i,1)
end
paddr = '0;
dut_req_port_o.data_req = '0;
dut_req_port_o.data_size = '0;
dut_req_port_o.data_be = '0;
dut_req_port_o.data_wdata = 'x;
endtask : genConstWrite
task automatic genWrapSeq();
automatic logic [63:0] val;
void'($urandom(RndSeed));
......@@ -258,6 +282,10 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #(
$display("%s> start linear sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i);
genSeqWrite();
end
CONST_SEQ: begin
$display("%s> start constant sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i);
genConstWrite();
end
WRAP_SEQ: begin
$display("%s> start wrapping sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i);
genWrapSeq();
......@@ -267,6 +295,9 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #(
$display("%s> start burst sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i);
genSeqBurst();
end
SET_SEQ: begin
$fatal(1, "Set sequence not implemented for write port agent.");
end
endcase // seq_type_i
seq_done_o = 1'b1;
$display("%s> stop sequence", PortName);
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment