chipyard: Add conditional traceport to top-level (#382)

* ariane: Add conditional rocket chip traceport to top-level
* ariane: Add license information

LICENSE.Berkeley

+BSD 3-Clause License
+
+Copyright (c) 2017-2020, The Regents of the University of California (Regents)
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+

include/traced_instr_pkg.sv

+// See LICENSE.Berkeley for license details.
+
+// Author: Abraham Gonzalez, UC Berkeley
+// Date: 24.02.2020
+// Description: Traced Instruction and Port (using in Rocket Chip based systems)
+
+package traced_instr_pkg;
+
+  typedef struct packed {
+      logic clock;
+      logic reset;
+      logic valid;
+      logic [63:0] iaddr;
+      logic [31:0] insn;
+      logic [1:0] priv;
+      logic exception;
+      logic interrupt;
+      logic [63:0] cause;
+      logic [63:0] tval;
+  } traced_instr_t;
+
+  typedef traced_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] trace_port_t;
+
+endpackage

src/ariane.sv

@@ -29,6 +29,10 @@ module ariane #(
   // Timer facilities
   input  logic                         time_irq_i,   // timer interrupt in (async)
   input  logic                         debug_req_i,  // debug request (async)
+`ifdef FIRESIM_TRACE
+  // firesim trace port
+  output traced_instr_pkg::trace_port_t trace_o,
+`endif
 `ifdef PITON_ARIANE
   // L15 (memory side)
   output wt_cache_pkg::l15_req_t       l15_req_o,
@@ -661,6 +665,23 @@ module ariane #(
   // -------------------
   // Instruction Tracer
   // -------------------
+
+  // Instruction trace port (used for FireSim)
+`ifdef FIRESIM_TRACE
+  for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_tp_connect
+    assign trace_o[i].clock = clk_i;
+    assign trace_o[i].reset = rst_ni;
+    assign trace_o[i].valid = commit_ack[i] & ~commit_instr_id_commit[i].ex.valid;
+    assign trace_o[i].iaddr = commit_instr_id_commit[i].pc;
+    assign trace_o[i].insn = commit_instr_id_commit[i].ex.tval[31:0];
+    assign trace_o[i].priv = priv_lvl;
+    assign trace_o[i].exception = commit_ack[i] & commit_instr_id_commit[i].ex.valid & ~commit_instr_id_commit[i].ex.cause[63];
+    assign trace_o[i].interrupt = commit_ack[i] & commit_instr_id_commit[i].ex.valid & commit_instr_id_commit[i].ex.cause[63];
+    assign trace_o[i].cause = commit_instr_id_commit[i].ex.cause;
+    assign trace_o[i].tval = commit_instr_id_commit[i].ex.tval[31:0];
+  end
+`endif
+
   //pragma translate_off
 `ifdef PITON_ARIANE
   localparam PC_QUEUE_DEPTH = 16;
@@ -799,4 +820,3 @@ module ariane #(
 //pragma translate_on
 
 endmodule // ariane
-