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Commit 5d9b7a15 authored by Alban Gruin's avatar Alban Gruin
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commit_stage: critical path improvements 


Signed-off-by: default avatarAlban Gruin <alban.gruin@irit.fr>
parent 04b25c4a
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with 25 additions and 49 deletions
src/commit_stage.sv
+ 25
− 49
View file @ 5d9b7a15
......@@ -92,22 +92,20 @@ module commit_stage import ariane_pkg::*; #(
always_comb begin : commit
// default assignments
commit_ack_o[0] = 1'b0;
commit_ack_o[1] = 1'b0;
amo_valid_commit_o = 1'b0;
// amo_valid_commit_o = 1'b0;
we_gpr_o[0] = 1'b0;
we_gpr_o[1] = 1'b0;
we_fpr_o = '{default: 1'b0};
commit_lsu_o = 1'b0;
commit_csr_o = 1'b0;
// commit_lsu_o = 1'b0;
// commit_csr_o = 1'b0;
// amos will commit on port 0
wdata_o[0] = (amo_resp_i.ack) ? amo_resp_i.result[riscv::XLEN-1:0] : commit_instr_i[0].result;
wdata_o[1] = commit_instr_i[1].result;
csr_op_o = ADD; // this corresponds to a CSR NOP
csr_wdata_o = {riscv::XLEN{1'b0}};
// csr_op_o = ADD; // this corresponds to a CSR NOP
// csr_wdata_o = {riscv::XLEN{1'b0}};
fence_i_o = 1'b0;
fence_o = 1'b0;
// fence_o = 1'b0;
sfence_vma_o = 1'b0;
csr_write_fflags_o = 1'b0;
flush_commit_o = 1'b0;
......@@ -128,7 +126,7 @@ module commit_stage import ariane_pkg::*; #(
// check if the LSU is ready to accept another commit entry (e.g.: a non-speculative store)
if (commit_lsu_ready_i) begin
commit_ack_o[0] = 1'b1;
commit_lsu_o = 1'b1;
// commit_lsu_o = 1'b1;
// stall in case the store buffer is not able to accept anymore instructions
end else begin
commit_ack_o[0] = 1'b0;
......@@ -139,7 +137,7 @@ module commit_stage import ariane_pkg::*; #(
// ---------
if (commit_instr_i[0].fu inside {FPU, FPU_VEC}) begin
// write the CSR with potential exception flags from retiring floating point instruction
csr_wdata_o = {{riscv::XLEN-5{1'b0}}, commit_instr_i[0].ex.cause[4:0]};
// csr_wdata_o = {{riscv::XLEN-5{1'b0}}, commit_instr_i[0].ex.cause[4:0]};
csr_write_fflags_o = 1'b1;
commit_ack_o[0] = 1'b1;
end
......@@ -150,10 +148,10 @@ module commit_stage import ariane_pkg::*; #(
// throw an exception
if (commit_instr_i[0].fu == CSR) begin
// write the CSR file
csr_op_o = commit_instr_i[0].op;
csr_wdata_o = commit_instr_i[0].result;
// csr_op_o = commit_instr_i[0].op;
// csr_wdata_o = commit_instr_i[0].result;
if (!csr_exception_i.valid) begin
commit_csr_o = 1'b1;
// commit_csr_o = 1'b1;
wdata_o[0] = csr_rdata_i;
commit_ack_o[0] = 1'b1;
end else begin
......@@ -193,7 +191,7 @@ module commit_stage import ariane_pkg::*; #(
if (commit_instr_i[0].op == FENCE) begin
commit_ack_o[0] = no_st_pending_i;
// tell the controller to flush the D$
fence_o = no_st_pending_i;
// fence_o = no_st_pending_i;
end
// ------------------
// AMO
......@@ -203,49 +201,27 @@ module commit_stage import ariane_pkg::*; #(
commit_ack_o[0] = amo_resp_i.ack;
// flush the pipeline
flush_commit_o = amo_resp_i.ack;
amo_valid_commit_o = 1'b1;
// amo_valid_commit_o = 1'b1;
we_gpr_o[0] = amo_resp_i.ack;
end
end
end
if (NR_COMMIT_PORTS > 1) begin
// -----------------
// Commit Port 2
// -----------------
// check if the second instruction can be committed as well and the first wasn't a CSR instruction
// also if we are in single step mode don't retire the second instruction
if (commit_ack_o[0] && commit_instr_i[1].valid
&& !halt_i
&& !(commit_instr_i[0].fu inside {CSR})
&& !flush_dcache_i
&& !instr_0_is_amo
&& !single_step_i) begin
// only if the first instruction didn't throw an exception and this instruction won't throw an exception
// and the functional unit is of type ALU, LOAD, CTRL_FLOW, MULT, FPU or FPU_VEC
if (!exception_o.valid && !commit_instr_i[1].ex.valid
&& (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin
logic can_commit_instr;
assign can_commit_instr = commit_instr_i[0].valid && !commit_instr_i[0].ex.valid && !halt_i;
if (is_rd_fpr(commit_instr_i[1].op))
we_fpr_o[1] = 1'b1;
else
we_gpr_o[1] = 1'b1;
assign csr_op_o = (can_commit_instr && commit_instr_i[0].fu == CSR) ? commit_instr_i[0].op : ADD;
assign csr_wdata_o = (can_commit_instr &&
commit_instr_i[0].fu inside {FPU, FPU_VEC}) ? {{riscv::XLEN-5{1'b0}}, commit_instr_i[0].ex.cause[4:0]} :
(can_commit_instr && commit_instr_i[0].fu == CSR) ? commit_instr_i[0].result :
{riscv::XLEN{1'b0}};
commit_ack_o[1] = 1'b1;
assign commit_csr_o = can_commit_instr && commit_instr_i[0].fu == CSR && !csr_exception_i.valid;
// additionally check if we are retiring an FPU instruction because we need to make sure that we write all
// exception flags
if (commit_instr_i[1].fu inside {FPU, FPU_VEC}) begin
if (csr_write_fflags_o)
csr_wdata_o = {{riscv::XLEN-5{1'b0}}, (commit_instr_i[0].ex.cause[4:0] | commit_instr_i[1].ex.cause[4:0])};
else
csr_wdata_o = {{riscv::XLEN-5{1'b0}}, commit_instr_i[1].ex.cause[4:0]};
assign commit_lsu_o = can_commit_instr && commit_instr_i[0].fu == STORE && !instr_0_is_amo && commit_lsu_ready_i;
assign amo_valid_commit_o = can_commit_instr && RVA && instr_0_is_amo;
csr_write_fflags_o = 1'b1;
end
end
end
end
end
assign fence_o = can_commit_instr && commit_instr_i[0].op == FENCE;
// -----------------------------
// Exception & Interrupt Logic
......
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