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Commit 64bda94d authored by sjthales's avatar sjthales
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update to implement cv32a6 on zybo z7-20 board

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Makefile
+ 16
− 1
View file @ 64bda94d
......@@ -288,7 +288,22 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
.PHONY: cva6_ooc
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga
cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream"
cd fpga && make cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
program_cva6_fpga:
@echo "[FPGA] Program FPGA"
cd fpga && make program_cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
clean:
rm -rf $(riscv-torture-dir)/output/test*
......
fpga/Makefile
+ 43
− 2
View file @ 64bda94d
......@@ -29,15 +29,46 @@
VIVADO ?= vivado
work-dir := work-fpga
bit := $(work-dir)/cva6_fpga.bit
ip-dir := xilinx
ips := xlnx_blk_mem_gen.xci \
xlnx_axi_clock_converter.xci \
xlnx_axi_dwidth_converter_dm_master.xci \
xlnx_axi_dwidth_converter_dm_slave.xci \
xlnx_clk_gen.xci
all: $(cva6_ooc)
cva6_ooc:
ifeq ($(BATCH_MODE), 1)
$(VIVADO) -mode batch -source scripts/run_cva6_ooc.tcl
else
$(VIVADO) -source scripts/run_cva6_ooc.tcl
$(VIVADO) -source scripts/run_cva6_ooc.tcl
endif
cva6_fpga: $(ips)
ifeq ($(BATCH_MODE), 1)
mkdir -p $(work-dir)
$(VIVADO) -mode batch -source scripts/run_cva6_fpga.tcl
else
$(VIVADO) -source scripts/run_cva6_fpga.tcl
endif
program_cva6_fpga:
ifeq ($(BATCH_MODE), 1)
$(VIVADO) -mode batch -source scripts/program_cva6_fpga.tcl
else
$(VIVADO) -source scripts/program_cva6_fpga.tcl
endif
$(ips): %.xci :
mkdir -p $(work-dir)
@echo Generating $(@F)
@cd $(ip-dir)/$(basename $(@F)) && make clean && make
@cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@
clean:
rm -rf *.log \
......@@ -45,15 +76,25 @@ clean:
*.str \
*.mif \
*.xpr \
*.xci \
cva6_ooc.cache \
cva6_ooc.hw \
cva6_ooc.ip_user_files \
cva6_ooc.sim \
cva6_ooc.runs \
cva6_ooc.hbs \
cva6_fpga.cache \
cva6_fpga.hw \
cva6_fpga.ip_user_files \
cva6_fpga.sim \
cva6_fpga.runs \
cva6_fpga.hbs \
.Xil \
reports_cva6_ooc_synth \
reports_cva6_ooc_impl
reports_cva6_ooc_impl \
reports_cva6_fpga_synth \
reports_cva6_fpga_impl \
$(work-dir)
.PHONY:
......
fpga/constraints/cva6_fpga.xdc 0 → 100644
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− 0
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## Common Ariane XDCs
create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
set_input_jitter tck 1.000
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
# minimize routing delay
set_input_delay -clock tck -clock_fall 5.000 [get_ports tdi]
set_input_delay -clock tck -clock_fall 5.000 [get_ports tms]
set_output_delay -clock tck 5.000 [get_ports tdo]
set_false_path -from [get_ports trst_n]
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
# set multicycle path on reset, on the FPGA we do not care about the reset anyway
set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
set_property MARK_DEBUG false [get_nets {debug_req[data][7]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][4]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][0]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][1]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][2]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][3]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][5]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][6]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][8]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][11]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][13]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][15]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][17]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][19]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][21]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][23]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][25]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][27]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][29]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][31]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][30]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][28]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][26]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][24]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][22]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][20]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][18]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][16]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][14]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][12]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][9]}]
set_property MARK_DEBUG false [get_nets {debug_req[data][10]}]
fpga/constraints/zybo_z7_20.xdc 0 → 100644
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set_property PACKAGE_PIN K17 [get_ports clk_sys]
set_property IOSTANDARD LVCMOS33 [get_ports clk_sys]
## Buttons
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports cpu_reset]
## To use FTDI FT2232 JTAG
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports trst_n]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports tck]
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports tdi]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports tdo]
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports tms]
## UART
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports tx]
set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports rx]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports tdo] 20.000
set_max_delay -from [get_ports tms] 20.000
set_max_delay -from [get_ports tdi] 20.000
set_max_delay -from [get_ports trst_n] 20.000
# reset signal
set_false_path -from [get_ports trst_n]
fpga/openocd_diligent_hs2.cfg 0 → 100644
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# Digilent JTAG-HS2
interface ftdi
ftdi_device_desc "Digilent USB Device"
ftdi_vid_pid 0x0403 0x6014
ftdi_serial 210249A85F9B
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
reset_config none
adapter_khz 1000
# TAP declaration
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba on
# dump jtag chain
scan_chain
bindto 0.0.0.0
init
halt
echo "Ready for Remote Connections"
fpga/scripts/program_cva6_fpga.tcl 0 → 100644
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open_hw
connect_hw_server
current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/210249A85F9B"}]
open_hw_target
set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7z020_1] 0]
set_property PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7z020_1]
set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
program_hw_devices [get_hw_devices xc7z020_1]
refresh_hw_device [lindex [get_hw_devices xc7z020_1] 0]
fpga/scripts/run_cva6_fpga.tcl 0 → 100644
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# Copyright (c) 2020 Thales.
#
# Copyright and related rights are licensed under the Solderpad
# License, Version 2.0 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# Author: Sebastien Jacq - sjthales on github.com
#
# Additional contributions by:
#
#
# script Name: run_cva6_fpga
# Project Name: CVA6 softcore
# Language: tcl
#
# Description: Script to generate bitstream of CVA6 architecture
# in Zybo 7-20 board
#
# =========================================================================== #
# Revisions :
# Date Version Author Description
# 2020-11-06 0.1 S.Jacq Created
# =========================================================================== #
set project cva6_fpga
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-4480]} -limit 1000
add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc
read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci
read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
source scripts/add_sources.tcl
set_property top cva6_zybo_z7_20 [current_fileset]
read_verilog -sv {src/zybo-z7-20.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/zybo-z7-20.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse constraints/$project.xdc
synth_design -rtl -name rtl_1
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
launch_runs synth_1
wait_on_run synth_1
open_run synth_1
exec mkdir -p reports_cva6_fpga_synth/
exec rm -rf reports_cva6_fpga_synth/*
check_timing -verbose -file reports_cva6_fpga_synth/$project.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_synth/$project.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_fpga_synth/$project.timing.rpt
report_utilization -hierarchical -file reports_cva6_fpga_synth/$project.utilization.rpt
report_cdc -file reports_cva6_fpga_synth/$project.cdc.rpt
report_clock_interaction -file reports_cva6_fpga_synth/$project.clock_interaction.rpt
# set for RuntimeOptimized implementation
set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
##create_clock -period $::env(CLK_PERIOD_NS) -name clk_i [get_ports clk_i]
#set_property HD.CLK_SRC BUFGCTRL_X1Y2 [get_ports clk_i]
launch_runs impl_1
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
# reports
exec mkdir -p reports_cva6_fpga_impl/
exec rm -rf reports_cva6_fpga_impl/*
check_timing -file reports_cva6_fpga_impl/${project}.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_impl/${project}.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_fpga_impl/${project}.timing.rpt
report_utilization -hierarchical -file reports_cva6_fpga_impl/${project}.utilization.rpt
fpga/src/ariane_peripherals_xilinx.sv
+ 1
− 1
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......@@ -308,7 +308,7 @@ module ariane_peripherals #(
// ---------------
// 3. SPI
// ---------------
assign spi.b_user = 1'b0;
//assign spi.b_user = 1'b0;
assign spi.r_user = 1'b0;
if (InclSPI) begin : gen_spi
......
fpga/src/ariane_xilinx.sv deleted 100644 → 0
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fpga/src/cva6_zybo_z7_20.sv 0 → 100644
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fpga/src/fan_ctrl.sv deleted 100644 → 0
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: PWM Fan Control for Genesys II board
// Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch
module fan_ctrl (
input logic clk_i,
input logic rst_ni,
input logic [3:0] pwm_setting_i,
output logic fan_pwm_o
);
logic [3:0] ms_clock_d, ms_clock_q;
logic [19:0] cycle_counter_d, cycle_counter_q;
// clock divider
always_comb begin
cycle_counter_d = cycle_counter_q;
ms_clock_d = ms_clock_q;
// divide clock by 499999
if (cycle_counter_q == 499_999) begin
cycle_counter_d = 0;
ms_clock_d = ms_clock_q + 1;
end else begin
cycle_counter_d = cycle_counter_q + 1;
end
if (ms_clock_q == 15) begin
ms_clock_d = 0;
end
end
// duty cycle
always_comb begin
if (ms_clock_q < pwm_setting_i) begin
fan_pwm_o = 1'b1;
end else begin
fan_pwm_o = 1'b0;
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
ms_clock_q <= '0;
cycle_counter_q <= '0;
end else begin
ms_clock_q <= ms_clock_d;
cycle_counter_q <= cycle_counter_d;
end
end
endmodule
fpga/src/genesysii.svh deleted 100644 → 0
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Set global FPGA degines
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define GENESYSII
// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
`define KINTEX7
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
fpga/src/kc705.svh deleted 100644 → 0
+ 0
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Set global FPGA degines
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define KC705
// include KINTEX7 specific code (relevant for KC705, GENESYSII,...)
`define KINTEX7
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
fpga/src/vc707.svh deleted 100644 → 0
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Set global FPGA degines
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define VC707
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
fpga/src/vcu118.svh deleted 100644 → 0
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// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Set global FPGA degines
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define VCU118
fpga/src/zybo-z7-20.svh
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......@@ -9,3 +9,6 @@
// write-through cache
`define WT_DCACHE
// debug probe
//`define LAUTERBACH_DEBUG_PROBE
fpga/xilinx/.gitignore 0 → 100644
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xlnx*/*
!xlnx*/tcl
!Makefile
!common.mk
!*.prj
\ No newline at end of file
fpga/xilinx/ariane_xlnx_ip.yml 0 → 100644
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xlnx_axi_dwidth_converter:
ip: axi_dwidth_converter
vendor: xilinx.com
config:
si_data_width: 64
si_id_width: 5
mi_data_width: 32
xlnx_axi_clock_converter:
ip: axi_clock_converter
vendor: xilinx.com
config:
width: 64
data_width: 64
id_width: 5
xlnx_axi_gpio:
ip: axi_gpio
vendor: xilinx.com
config:
c_gpio_width: 8
c_gpio2_width: 8
c_is_dual: 1
c_all_inputs_2: 1
c_interrupt_present: 0
xlnx_axi_quad_spi:
ip: axi_quad_spi
vendor: xilinx.com
config:
c_use_startup: 0
c_sck_ratio: 4
c_fifo_depth: 256
c_type_of_axi4_interface: 1
c_s_axi4_id_width: 0
xlnx_clk_gen:
ip: clk_wiz
vendor: xilinx.com
config:
prim_in_freq: 200
num_out_clks: 4
clkout2_used: true
clkout3_used: true
clkout4_used: true
clkout1_requested_out_freq: 50
clkout2_requested_out_freq: 125
clkout3_requested_out_freq: 125
clkout3_requested_phase: 90
clkout4_requested_out_freq: 50
clkin1_jitter_ps: 50
xlnx_ila:
ip: ila
vendor: xilinx.com
config:
c_num_of_probes: 8
c_probe3_width: 4
c_probe6_width: 4
c_data_depth: 16384
c_input_pipe_stages: 1
xlnx_mig_7_ddr3:
ip: mig_7series
vendor: xilinx.com
config:
xml_input_file: mig_a.prj
reset_board_interface: Custom
mig_dont_touch_param: Custom
board_mig_param: Custom
xlnx_ila:
ip: xlnx_ila
vendor: xilinx.com
config:
addr_width: 64
data_width: 64
id_width: 5
awuser_width: 1
aruser_width: 1
ruser_width: 1
wuser_width: 1
buser_width: 1
max_aw_waits: 1024
max_ar_waits: 1024
max_w_waits: 1024
max_r_waits: 1024
max_b_waits: 1024
max_continuous_wtransfers_waits: 1024
max_wlast_to_awvalid_waits: 1024
max_write_to_bvalid_waits: 1024
max_continuous_rtransfers_waits: 1024
\ No newline at end of file
fpga/xilinx/common.mk 0 → 100644
+ 19
− 0
View file @ 64bda94d
all:
vivado -mode batch -source tcl/run.tcl
mkdir -p ip
cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
gui:
vivado -mode gui -source tcl/run.tcl &
clean:
rm -rf ip/*
mkdir -p ip
rm -rf ${PROJECT}.*
rm -rf component.xml
rm -rf vivado*.jou
rm -rf vivado*.log
rm -rf vivado*.str
rm -rf xgui
rm -rf .Xil
\ No newline at end of file
fpga/xilinx/xlnx_axi_clock_converter/Makefile 0 → 100644
+ 2
− 0
View file @ 64bda94d
PROJECT:=xlnx_axi_clock_converter
include ../common.mk
\ No newline at end of file
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