wt_axi_adapter: base logic for better arbitration in case of loads

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/cache_subsystem/wt_axi_adapter.sv

@@ -84,6 +84,11 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
   logic dcache_rd_full, dcache_rd_empty;
   logic dcache_wr_full, dcache_wr_empty;
 
+  logic dcache_awaits_loads;
+  logic dcache_has_no_loads;
+
+  assign dcache_awaits_loads = ~dcache_has_no_loads;
+
   assign icache_data_ack_o  = icache_data_req_i & ~icache_data_full;
   assign dcache_data_ack_o  = dcache_data_req_i & ~dcache_data_full;
 
@@ -263,6 +268,23 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
     .pop_i       (  arb_ack[1]              )
   );
 
+  fifo_v3 #(
+    .dtype (logic),
+    .DEPTH (ReqFifoDepth)
+  ) i_dcache_load_fifo (
+    .clk_i (clk_i),
+    .rst_ni (rst_ni),
+    .flush_i (1'b0),
+    .testmode_i (1'b0),
+    .full_o (),
+    .empty_o (dcache_has_no_loads),
+    .usage_o (),
+    .data_i (1'b1),
+    .push_i (dcache_data_ack_o & (dcache_data_i.rtype == wt_cache_pkg::DCACHE_LOAD_REQ)),
+    .data_o (),
+    .pop_i (arb_ack[1] & (dcache_data.rtype == wt_cache_pkg::DCACHE_LOAD_REQ))
+  );
+
 ///////////////////////////////////////////////////////
 // meta info feedback fifos
 ///////////////////////////////////////////////////////