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MINOTAuR
printemps
Commits
8b6f6f93
Commit
8b6f6f93
authored
4 years ago
by
Alban Gruin
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verifier: base verifier
Signed-off-by:
Alban Gruin
<
alban.gruin@irit.fr
>
parent
0abb1a6d
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src/ariane.sv
+16
-0
16 additions, 0 deletions
src/ariane.sv
src/verifier.sv
+61
-0
61 additions, 0 deletions
src/verifier.sv
with
77 additions
and
0 deletions
src/ariane.sv
+
16
−
0
View file @
8b6f6f93
...
...
@@ -606,6 +606,22 @@ module ariane import ariane_pkg::*; #(
.
*
);
// ----------
// Verifier
// ----------
verifier
#(
.
NR_ENTRIES
(
NR_SB_ENTRIES
),
.
NR_COMMIT_PORTS
(
NR_COMMIT_PORTS
)
)
verifier_i
(
.
clk_i
,
.
rst_ni
,
.
flush_i
(
flush_ctrl_id
),
// CO
.
commit_instr_i
(
commit_instr_id_commit
),
.
commit_ack_i
(
commit_ack
)
);
// -------------------
// Cache Subsystem
// -------------------
...
...
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src/verifier.sv
0 → 100644
+
61
−
0
View file @
8b6f6f93
module
verifier
#(
parameter
int
unsigned
NR_ENTRIES
=
8
,
parameter
int
unsigned
NR_COMMIT_PORTS
=
2
)
(
input
logic
clk_i
,
input
logic
rst_ni
,
input
logic
flush_i
,
// CO
input
ariane_pkg
::
scoreboard_entry_t
[
NR_COMMIT_PORTS
-
1
:
0
]
commit_instr_i
,
input
logic
[
NR_COMMIT_PORTS
-
1
:
0
]
commit_ack_i
);
localparam
int
unsigned
BITS_ENTRIES
=
$
clog2
(
NR_ENTRIES
);
// CO
logic
[
NR_COMMIT_PORTS
-
1
:
0
][
BITS_ENTRIES
-
1
:
0
]
commit_id_n
,
commit_id_q
;
logic
[
NR_COMMIT_PORTS
-
1
:
0
]
commit_correct
;
logic
[
BITS_ENTRIES
-
1
:
0
]
commit_nr
;
popcount
#(
.
INPUT_WIDTH
(
NR_COMMIT_PORTS
)
)
(
.
data_i
(
commit_ack_i
),
.
popcount_o
(
commit_nr
)
);
assign
commit_id_n
[
0
]
=
(
flush_i
)
?
'0
:
commit_id_q
[
0
]
+
commit_nr
;
for
(
genvar
i
=
1
;
i
<
NR_COMMIT_PORTS
;
i
++
)
begin
assign
commit_id_n
[
i
]
=
(
flush_i
)
?
'0
:
commit_id_n
[
0
]
+
i
;
end
for
(
genvar
i
=
0
;
i
<
NR_COMMIT_PORTS
;
i
++
)
begin
assign
commit_correct
[
i
]
=
!
(
commit_instr_i
[
i
].
valid
)
||
(
commit_instr_i
[
i
].
valid
&
commit_instr_i
[
i
].
trans_id
==
commit_id_q
[
i
]);
end
always_ff
@
(
posedge
clk_i
or
negedge
rst_ni
)
begin
:
regs
if
(
!
rst_ni
)
begin
commit_id_q
<=
'0
;
end
else
begin
commit_id_q
<=
commit_id_n
;
end
end
//pragma translate off
`ifndef
VERILATOR
initial
begin
assert
(
NR_ENTRIES
==
2
**
BITS_ENTRIES
)
else
$
fatal
(
"NR_ENTRIES is not a power of 2"
);
end
for
(
genvar
i
=
0
;
i
<
NR_COMMIT_PORTS
;
i
++
)
begin
assert
property
(
@
(
posedge
clk_i
)
disable
iff
(
!
rst_ni
)
commit_ack_i
[
i
]
|->
commit_correct
[
i
])
else
$
warning
(
1
,
"Invalid commit"
);
end
`endif
//pragma translate on
endmodule
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