Skip to content
Snippets Groups Projects
Unverified Commit 8e3294a1 authored by sébastien jacq's avatar sébastien jacq Committed by GitHub
Browse files

Merge pull request #2 from atrogerTHALES/master

Corrections before contest
parents c6a30ad5 9a42b7a3
No related branches found
No related tags found
No related merge requests found
...@@ -45,7 +45,7 @@ To do so, **Vitis 2020.1** environment from Xilinx need to be installed. ...@@ -45,7 +45,7 @@ To do so, **Vitis 2020.1** environment from Xilinx need to be installed.
Furthermore, Digilent provides board files for each development board. Furthermore, Digilent provides board files for each development board.
This files ease the creating of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces. This files ease the creation of new projects with automated configuration of several complicated components such as Zynq Processing System and memory interfaces.
All guidelines to install **vitis 2020.1** and **Zybo 7-20** board files are explained to the following link: All guidelines to install **vitis 2020.1** and **Zybo 7-20** board files are explained to the following link:
https://reference.digilentinc.com/reference/programmable-logic/guides/installation https://reference.digilentinc.com/reference/programmable-logic/guides/installation
...@@ -87,7 +87,7 @@ In the first time, synthesis and place and route are carried in out of context m ...@@ -87,7 +87,7 @@ In the first time, synthesis and place and route are carried in out of context m
That allows to have an estimation of the logical resources used by the CVA6 in the FPGA fabric as well as the maximal frequency of CVA6 architecture. That allows to have an estimation of the logical resources used by the CVA6 in the FPGA fabric as well as the maximal frequency of CVA6 architecture.
These both metrics are majors for a computation architecture. They are both major metrics for a computation architecture.
Command to run for synthesis and place and route in out of context mode: Command to run for synthesis and place and route in out of context mode:
``` ```
......
...@@ -9,16 +9,16 @@ ...@@ -9,16 +9,16 @@
/* This linker script is adapted from the default linker script for upstream /* This linker script is adapted from the default linker script for upstream
RISC-V GCC. It has been modified for use in verification of CORE-V cores. RISC-V GCC. It has been modified for use in verification of CORE-V cores.
*/ */
// Additional contributions by: /* Additional contributions by:
// Sebastien Jacq - sjthales on github.com Sebastien Jacq - sjthales on github.com
//
// Description: linkerscript for the CV32A6 platform Description: linkerscript for the CV32A6 platform
//
// =========================================================================== // ===========================================================================
// Revisions : Revisions :
// Date Version Author Description Date Version Author Description
// 2020-10-06 0.1 S.Jacq modification of the Test for CV32A6 softcore 2020-10-06 0.1 S.Jacq modification of the Test for CV32A6 softcore
// =========================================================================== // =========================================================================== */
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
"elf32-littleriscv") "elf32-littleriscv")
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment