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  • experimental
  • printemps-vcu118 default protected
  • printemps-zcu104
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Created with Raphaël 2.2.023Jun18Oct16Nov6May2Mar19Feb814Jan11May19Mar178Jan515Dec87429Oct2827261615141312911Sep108228Aug2726252429Jul26161421Jun16231May181529Apr2826151414Mar1327Feb261810422Jan13Dec323Oct119827Sep1220Aug191214Jul12104Jun20Mar191818Feb1514876531Jan30292825242315129874Dec229Nov2827262523222120191817161513128765432131Oct302926251918171615141310987329Sep282726252432 bits FPU can be synthesized and seems to work on target.experimentalexperimentalExperimental branch with FPU enabledREADME updated, constraints vcu118 addedprintemps-vcu11…printemps-vcu118 printemps-zcu104Fixed README.mdFixed README.mdmodified README.mdFirst commit for Minotaur with LRU and RAS on vcu118sythesis works for vcu118 and coremarks runfpga: port Ariane to the Ultrascale ZCU104frontend: remove usage of opaque module `unread'frontend: fix branch prediction commitMakefile: add SyncDpRam and SyncTpRamissue stage: critical path improvementscommit_stage: critical path improvementsverifier: remove useless stuffscoreboard: don't commit pending instructions when when flushingcsr_buffer: critical path improvements (?)fixup! scoreboard: size and timing improvementsscoreboard: size and timing improvementsfixup! ex_stage, issue_stage: add a dedicated bus for the MULTex_stage, issue_stage: add a dedicated bus for the MULTRevert "ex_stage: add an arbitrer to the FLU bus"IRO: always allow an ALU instruction to be executedex_stage: add an arbitrer to the FLU busscoreboard: accept instructions even if they will not be issued next cycleariane_pkg: use a single commit portariane: route dcache_load_delayed to perf_counterscache_subsystem: add signal dcache_load_delayedfrontend: remove ugly instr_fifowt_axi_adapter: base logic for better arbitration in case of loadsverifier: add assert to check for concurrent bus accessesperf_counters: add perf counters to check for SIC violations[WIP] cache: add a signal to stall the I$verifier: hook up signal from the store bufferverifier: add a signal to lock I$ requestsverifier: add I$ misses to its inputsscoreboard: scan the scoreboard for memory operationsdecoder: add logic output to say if there is a memory instructioninstr_queue: instr_fifofrontend: add memory access instructions detection