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MINOTAuR
printemps
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bd97d18c162dd4732be2a52e29701cb37b7e43c4
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bd97d18c162dd4732be2a52e29701cb37b7e43c4
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printemps-vcu118
default
protected
block-design
experimental
experimental-block-design
printemps-zcu104
6 results
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Created with Raphaël 2.2.0
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Sep
Fixed typos
experimental-bl…
experimental-block-design
Fixed typos in wrappers
Added wrappers for plic
added uart wrapper
Fixed AXI interface sizes. Core seems to run properly with JTAG.
handled atomics, added commented ILA
Fixed axi interface, added unread.sv
block-design
block-design
fixed typos
Fixed axi interface, added unread.sv
fixed typos
Updated wrappers for block design
removed wrong port from clint_wrapper
small name fix
Corrected wrappers for clint
Added wrappers for clint. To be tested in vivado.
Verilog wrapper interface modifications for vivado block design
Added block design files
Updated wrappers for block design
removed wrong port from clint_wrapper
small name fix
Corrected wrappers for clint
Added wrappers for clint. To be tested in vivado.
Verilog wrapper interface modifications for vivado block design
Added block design files
32 bits FPU can be synthesized and seems to work on target.
experimental
experimental
Experimental branch with FPU enabled
README updated, constraints vcu118 added
printemps-vcu11…
printemps-vcu118 printemps-zcu104
Fixed README.md
Fixed README.md
modified README.md
First commit for Minotaur with LRU and RAS on vcu118
sythesis works for vcu118 and coremarks run
fpga: port Ariane to the Ultrascale ZCU104
frontend: remove usage of opaque module `unread'
frontend: fix branch prediction commit
Makefile: add SyncDpRam and SyncTpRam
issue stage: critical path improvements
commit_stage: critical path improvements
verifier: remove useless stuff
scoreboard: don't commit pending instructions when when flushing
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