Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
P
printemps
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
MINOTAuR
printemps
Repository
printemps-vcu118
Select Git revision
Branches
3
experimental
printemps-vcu118
default
protected
printemps-zcu104
3 results
printemps
src
Find file
Code
Clone with SSH
Clone with HTTPS
Open in your IDE
Visual Studio Code (SSH)
Visual Studio Code (HTTPS)
IntelliJ IDEA (SSH)
IntelliJ IDEA (HTTPS)
Download source code
zip
tar.gz
tar.bz2
tar
Download this directory
zip
tar.gz
tar.bz2
tar
Download
Download source code
zip
tar.gz
tar.bz2
tar
Copy HTTPS clone URL
Copy SSH clone URL
git@gitlab.irit.fr:minotaur/printemps.git
Copy HTTPS clone URL
https://gitlab.irit.fr/minotaur/printemps.git
First commit for Minotaur with LRU and RAS on vcu118
tcarle
authored
8 months ago
2dd26b30
History
2dd26b30
8 months ago
History
Name
Last commit
Last update
..
cache_subsystem
clint
frontend
pmp
util
axi
@
3f5d5b54
axi_mem_if
@
4650ca90
axi_node
@
a29a69a5
axi_riscv_atomics
@
550881f1
common_cells
@
b2a4b2d3
fpga-support
@
a3ba269c
fpu
@
79f75e0a
register_interface
@
d8aeccc6
riscv-dbg
@
6d768ac6
rv_plic
@
ebe3e988
tech_cells_generic
@
ffe7818d
alu.sv
amo_buffer.sv
ariane.sv
ariane_regfile.sv
ariane_regfile_ff.sv
axi_adapter.sv
axi_adapter_32.sv
axi_shim.sv
branch_unit.sv
commit_stage.sv
compressed_decoder.sv
controller.sv
csr_buffer.sv
csr_regfile.sv
decoder.sv
dromajo_ram.sv
ex_stage.sv
fpu_wrap.sv
id_stage.sv
instr_realign.sv
issue_read_operands.sv
issue_stage.sv
load_store_unit.sv
load_unit.sv
mmu.sv
mult.sv
multiplier.sv
perf_counters.sv
ptw.sv
re_name.sv
scoreboard.sv
serdiv.sv
store_buffer.sv
store_unit.sv
tlb.sv
verifier.sv