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Commit 247d11ef authored by sjthales's avatar sjthales
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updating README to implement CV32A6 on Zybo z7-20 board

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...@@ -63,6 +63,8 @@ https://reference.digilentinc.com/reference/programmable-logic/guides/installati ...@@ -63,6 +63,8 @@ https://reference.digilentinc.com/reference/programmable-logic/guides/installati
**be careful about your linux distribution and the supported version of Vitis 2020.1 environment** **be careful about your linux distribution and the supported version of Vitis 2020.1 environment**
## Hardware
If you have not yet done so, start provisioning the following: If you have not yet done so, start provisioning the following:
| Reference | URL | List price | Remark | | Reference | URL | List price | Remark |
...@@ -73,7 +75,91 @@ If you have not yet done so, start provisioning the following: ...@@ -73,7 +75,91 @@ If you have not yet done so, start provisioning the following:
| Connectors | https://store.digilentinc.com/pmod-cable-kit-2x6-pin-and-2x6-pin-to-dual-6-pin-pmod-splitter-cable/ | $5.99 | At least a 6-pin connector Pmod is necessary; other references may offer it. | | Connectors | https://store.digilentinc.com/pmod-cable-kit-2x6-pin-and-2x6-pin-to-dual-6-pin-pmod-splitter-cable/ | $5.99 | At least a 6-pin connector Pmod is necessary; other references may offer it. |
## Simulation get started ## OpenOCD
To be able to run and debug software applications on CVA6, you need to install OpenOCD tool.
OpenOCD is a free and open-source software distributed under the GPL-2.0 license.
It provides on-chip programming and debugging support with a layered architecture of JTAG interface and TAP support.
Global documentation on OpenOCD is available at https://github.com/ThalesGroup/pulpino-compliant-debug/tree/pulpino-dbg/doc/riscv-debug-notes/pdfs
Theses documents aim at providing help about OpenOCD and RISC-V debug.
Before setting up OpenOCD, other tools are needed:
- make
- libtool
- pkg-congfig > 0.23
- autoconf > 2.64
- automake > 1.14
- texinfo
On Ubuntu, ensure that everything is installed with:
```
$ sudo apt install make libtool pkg-config autoconf automake texinfo
```
Furthermore, you need to set up libusb and libftdi libraries.
On Ubuntu:
```
$ sudo apt install libusb-1.0-0-dev libftdi1-dev
```
Once all dependencies are installed, OpenOCD can be set up.
- Download sources:
```
$ git clone https://github.com/riscv/riscv-openocd
$ cd riscv-openocd
```
- Prepare a **build** directory:
```
$ mkdir build
```
- Launch the bootstrap scipt:
```
$ ./bootstrap
```
- Launch configure:
```
$ ./configure --enable-ftdi --prefix=build --exec-prefix=build
```
- Compile and install files:
```
$ make
$ make install
```
When the installation is achieved, do not forget to add riscv-openocd/build/bin to your PATH.
```
$ export PATH=$PATH:<path to riscv-openocd>/build/bin
```
## HS2 cable
It is necessary to add a udev rule to use the cable.
OpenOCD provides a file containing the rule we need. Copy it into /etc/udev/rules.d/
```
$ sudo cp <openocd>/contrib/60-openocd.rules /etc/udev/rules.d
```
The file is also available here: https://github.com/riscv/riscv-openocd/blob/riscv/contrib/60-openocd.rules
The particular entry about the HS2 cable is :
```
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="660", GROUP="plugdev", TAG+="uaccess"
```
Then either reboot your system or reload the udev configuration with :
```
$ sudo udevadm control --reload
```
To check if the cable is recognized, run lsusb. There should be a line like this:
```
$ lsusb
```
```
Bus 005 Device 003: ID 0403:6014 Future Technology Devices International, Ltd FT232HSingle HS USB-UART/FIFO IC
```
# Simulation get started
When the development environment is set up, it is now possible to run a simulation. When the development environment is set up, it is now possible to run a simulation.
Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and Coremark and other test applications. Some software applications are available into the sw/app directory. Especially, there are benchmark applications such as Dhrystone and Coremark and other test applications.
...@@ -136,4 +222,109 @@ $ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0 ...@@ -136,4 +222,109 @@ $ make cva6_ooc CLK_PERIOD_NS=20 BATCH_MODE=0
This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**. This command generates synthesis and place and route reports in **fpga/reports_cva6_ooc_synth** and **fpga/reports_cva6_ooc_impl**.
# FPGA emulation
A FPGA platform emulating **CV32A6** (CVA6 in 32b flavor) has been implemented on **Zybo Z7-20** board.
This platform consists of a CV32A6 processor, a JTAG interface to run and debug software applications and a UART interface to display strings on hyperterminal.
Below is described steps to run Coremark application on CV32A6 FPGA platform, steps are the same for Dhrystone application and others software applications.
## Get started with Coremark application
1. First, make sure the digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBAUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
2. compile coremark application in `sw/app`
3. Generate the bitstream of the FPGA platform:
```
$ make cva6_fpga
```
4. When bistream is generated, switch on Zybo board and run:
```
$ make program_cva6_fpga
```
5. then, in a terminal, launch **OpenOCD**:
```
$ openocd -f fpga/openocd_digilent_hs2.cfg
```
If it is succesful, you should see something like that:
```
Open On-Chip Debugger 0.10.0+dev-00832-gaec5cca (2019-12-10-14:21)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x249511c3 (mfg: 0x0e1 (Wintec Industries), part: 0x4951, ver: 0x2)
Info : datacount=2 progbufsize=8
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40141105
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
```
6. In separate terminal, launch **gdb**:
```
$ riscv32-unknown-elf-gdb sw/app/coremark.riscv
```
you must use gdb of the RISC-V toolchain. If it is succesful, you should see:
```
GNU gdb (GDB) 9.1
Copyright (C) 2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv32-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from sw/app/coremark.riscv...
(gdb)
```
7. In gdb, you need to connect gdb to openocd:
```
(gdb) target remote :3333
```
if it is successful, you should see the gdb connection in openocd:
```
Info : accepting 'gdb' connection on tcp/3333
```
8. In gdb, load **coremark.riscv** to CV32A6 FPGA platform:
```
(gdb) load
Loading section .vectors, size 0x80 lma 0x80000000
Loading section .init, size 0x60 lma 0x80000080
Loading section .text, size 0x19010 lma 0x800000e0
Loading section .rodata, size 0x1520 lma 0x800190f0
Loading section .eh_frame, size 0x50 lma 0x8001a610
Loading section .init_array, size 0x4 lma 0x8001a660
Loading section .data, size 0x9d4 lma 0x8001a668
Loading section .sdata, size 0x40 lma 0x8001b040
Start address 0x80000080, load size 110712
Transfer rate: 63 KB/sec, 7908 bytes/write.
```
9. At last, in gdb, you can run the coremark application by command `c`:
```
(gdb) c
Continuing.
(gdb)
```
10. On hyperterminal configured on /dev/ttyUSB0 11520-8-N-1, you should see:
```
2K performance run parameters for coremark.
....
CoreMark 1.0 :
```
docs/pictures/20201204_150708.jpg

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docs/pictures/20201204_160542.jpg

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open_hw open_hw_manager
connect_hw_server connect_hw_server
current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/210249A85F9B"}] current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/210249A85F9B"}]
open_hw_target open_hw_target
......
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