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MINOTAuR
MINOTAuR
Commits
33682980
Commit
33682980
authored
4 years ago
by
Alban Gruin
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wt_icache: lock requests
Signed-off-by:
Alban Gruin
<
alban.gruin@irit.fr
>
parent
59a05d40
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src/cache_subsystem/wt_icache.sv
+2
-2
2 additions, 2 deletions
src/cache_subsystem/wt_icache.sv
with
2 additions
and
2 deletions
src/cache_subsystem/wt_icache.sv
+
2
−
2
View file @
33682980
...
@@ -197,7 +197,7 @@ end else begin : gen_piton_offset
...
@@ -197,7 +197,7 @@ end else begin : gen_piton_offset
// wait for incoming requests
// wait for incoming requests
end
else
begin
end
else
begin
// mem requests are for sure invals here
// mem requests are for sure invals here
if
(
!
mem_rtrn_vld_i
)
begin
if
(
!
mem_rtrn_vld_i
&&
!
stall_req_i
)
begin
dreq_o
.
ready
=
1'b1
;
dreq_o
.
ready
=
1'b1
;
// we have a new request
// we have a new request
if
(
dreq_i
.
req
)
begin
if
(
dreq_i
.
req
)
begin
...
@@ -250,7 +250,7 @@ end else begin : gen_piton_offset
...
@@ -250,7 +250,7 @@ end else begin : gen_piton_offset
// we have a miss / NC transaction
// we have a miss / NC transaction
end
else
if
(
dreq_i
.
kill_s2
)
begin
end
else
if
(
dreq_i
.
kill_s2
)
begin
state_d
=
IDLE
;
state_d
=
IDLE
;
end
else
begin
end
else
if
(
!
stall_req_i
)
begin
cmp_en_d
=
1'b0
;
cmp_en_d
=
1'b0
;
// only count this as a miss if the cache is enabled, and
// only count this as a miss if the cache is enabled, and
// the address is cacheable
// the address is cacheable
...
...
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