Small SoC modifications

.editorconfig

@@ -6,8 +6,8 @@ root = true
 end_of_line = lf
 insert_final_newline = true
 trim_trailing_whitespace = true
-max_line_length = off
+max_line_length = 100
 # 4 space indentation
 [*.{sv, svh, v, vhd}]
 indent_style = space
-indent_size = 4
+indent_size = 2

fpga/src/ariane_peripherals.sv

@@ -74,10 +74,10 @@ module ariane_peripherals #(
         .clk_i              ( clk_i                  ),
         .rst_ni             ( rst_ni                 ),
         .irq_sources_i      ( irq_sources            ),
-        .eip_targets_o      ( irq_o                  ),
+        .eip_targets_o      (                   ),
         .external_bus_io    ( reg_bus                )
     );
-
+    assign irq_o = '0;
     // ---------------
     // UART
     // ---------------
@@ -432,4 +432,4 @@ module ariane_peripherals #(
         assign s_axi_spi_rlast = 1'b1;
         assign s_axi_spi_rvalid = 1'b1;
     end
-endmodule
+endmodule
\ No newline at end of file

fpga/src/bootrom/ariane.dts

@@ -5,9 +5,9 @@
   #size-cells = <2>;
   compatible = "eth,ariane-bare-dev";
   model = "eth,ariane-bare";
-  chosen {
-    stdout-path = "/soc/uart@10000000:115200";
-  };
+  // chosen {
+  //   stdout-path = "/soc/uart@10000000:115200";
+  // };
   cpus {
     #address-cells = <1>;
     #size-cells = <0>;

src/decoder.sv

@@ -108,7 +108,7 @@ module decoder (
                                     if (priv_lvl_i == riscv::PRIV_LVL_S && tsr_i) begin
                                         illegal_instr = 1'b1;
                                         //  do not change privilege level if this is an illegal instruction
-                                       instruction_o.op = ADD;
+                                        instruction_o.op = ADD;
                                     end
                                 end
                                 // MRET

src/mmu.sv

@@ -156,6 +156,25 @@ module mmu #(
         .*
      );
 
+    ila_1 i_ila_1 (
+        .clk(clk_i), // input wire clk
+        .probe0({req_port_o.address_tag, req_port_o.address_index}),
+        .probe1(req_port_o.data_req), // input wire [63:0]  probe1
+        .probe2(req_port_i.data_gnt), // input wire [0:0]  probe2
+        .probe3(req_port_i.data_rdata), // input wire [0:0]  probe3
+        .probe4(req_port_i.data_rvalid), // input wire [0:0]  probe4
+        .probe5(ptw_error), // input wire [1:0]  probe5
+        .probe6(update_vaddr), // input wire [0:0]  probe6
+        .probe7(update_ptw_itlb.valid), // input wire [0:0]  probe7
+        .probe8(update_ptw_dtlb.valid), // input wire [0:0]  probe8
+        .probe9(dtlb_lu_access), // input wire [0:0]  probe9
+        .probe10(lsu_vaddr_i), // input wire [0:0]  probe10
+        .probe11(dtlb_lu_hit), // input wire [0:0]  probe11
+        .probe12(itlb_lu_access), // input wire [0:0]  probe12
+        .probe13(icache_areq_i.fetch_vaddr), // input wire [0:0]  probe13
+        .probe14(itlb_lu_hit) // input wire [0:0]  probe13
+    );
+
     //-----------------------
     // Instruction Interface
     //-----------------------