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verilator: Add memory preloading
Pre-load the Verilator memories through a side-band signal. We have sub-classed
the dtm_t module to prevent the debugger from pre-loading. This commit also
updates the stale bootrom.
Signed-off-by:
Florian Zaruba <florian@openhwgroup.org>
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- Makefile 1 addition, 1 deletionMakefile
- bootrom/bootrom.S 2 additions, 3 deletionsbootrom/bootrom.S
- bootrom/bootrom.h 73 additions, 45 deletionsbootrom/bootrom.h
- bootrom/bootrom.img 0 additions, 0 deletionsbootrom/bootrom.img
- bootrom/bootrom.sv 45 additions, 31 deletionsbootrom/bootrom.sv
- ci/riscv-asm-tests.list 33 additions, 5 deletionsci/riscv-asm-tests.list
- ci/riscv-mul-tests.list 12 additions, 12 deletionsci/riscv-mul-tests.list
- tb/ariane_tb.cpp 27 additions, 1 deletiontb/ariane_tb.cpp
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