Update Makefile with path to ethernet submodule Verilog files

Makefile

@@ -142,7 +142,7 @@ src := $(addprefix $(root-dir), $(src))
 uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
-fpga_src :=  $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv)
+fpga_src :=  $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
 fpga_src := $(addprefix $(root-dir), $(fpga_src))
 
 # look for testbenches

ariane-ethernet @ 4ea1127e

-Subproject commit c8fd89437d250b59ead30c233cf2a279be1c48c7
+Subproject commit 4ea1127e5d2d0b5d3bd281542066b4a4e4d2fe50