Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
M
MINOTAuR
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
MINOTAuR
MINOTAuR
Commits
549281aa
Commit
549281aa
authored
4 years ago
by
Alban Gruin
Browse files
Options
Downloads
Patches
Plain Diff
ariane: lock I$ requests if there is a CF in the pipeline
Signed-off-by:
Alban Gruin
<
alban.gruin@irit.fr
>
parent
7d26784a
Branches
minotaur_beta
Branches containing commit
Tags
Tags containing commit
No related merge requests found
Pipeline
#458
failed
3 years ago
Stage: build
Stage: write-back
Stage: write-through
Changes
2
Pipelines
1
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
src/ariane.sv
+3
-0
3 additions, 0 deletions
src/ariane.sv
src/verifier.sv
+5
-1
5 additions, 1 deletion
src/verifier.sv
with
8 additions
and
1 deletion
src/ariane.sv
+
3
−
0
View file @
549281aa
...
...
@@ -655,12 +655,15 @@ module ariane import ariane_pkg::*; #(
// IF
.
if_has_mem_access_i
(
has_mem_access_if_verif
),
.
if_has_cf_i
(
has_ctrl_flow_if_icache
),
// ID
.
id_has_mem_access_i
(
has_mem_access_id_verif
),
.
id_has_cf_i
(
has_ctrl_flow_id_icache
),
// IS
.
is_has_mem_access_i
(
has_mem_access_is_verif
),
.
is_has_cf_i
(
has_ctrl_flow_is_icache
),
// LSU
.
no_st_pending_commit_i
(
no_st_pending_ex
),
...
...
This diff is collapsed.
Click to expand it.
src/verifier.sv
+
5
−
1
View file @
549281aa
...
...
@@ -11,12 +11,15 @@ module verifier #(
// Frontend
input
logic
if_has_mem_access_i
,
input
logic
if_has_cf_i
,
// ID
input
logic
id_has_mem_access_i
,
input
logic
id_has_cf_i
,
// IS
input
logic
is_has_mem_access_i
,
input
logic
is_has_cf_i
,
// LSU
input
logic
no_st_pending_commit_i
,
...
...
@@ -33,8 +36,9 @@ module verifier #(
// Bus accesses (I$ misses and memory instructions in the pipeline)
logic
has_mem_access
;
assign
has_mem_access
=
if_has_mem_access_i
|
id_has_mem_access_i
|
is_has_mem_access_i
|
(
~
no_st_pending_commit_i
);
// assign should_lock_icache_o = has_mem_access & icache_miss_i;
assign
should_lock_icache_o
=
has_mem_access
;
assign
should_lock_icache_o
=
has_mem_access
|
if_has_cf_i
|
id_has_cf_i
|
is_has_cf_i
;
// CO
logic
[
NR_COMMIT_PORTS
-
1
:
0
][
BITS_ENTRIES
-
1
:
0
]
commit_id_n
,
commit_id_q
;
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment