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Commit 562b13a7 authored by Alban Gruin's avatar Alban Gruin
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Revert "verifier: lock I$ on D$ writes"

This reverts commit aaccf475.
parent 0753e342
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...@@ -108,8 +108,6 @@ module ariane import ariane_pkg::*; #( ...@@ -108,8 +108,6 @@ module ariane import ariane_pkg::*; #(
logic has_mem_access_is_verif; logic has_mem_access_is_verif;
logic has_ctrl_flow_is_icache; logic has_ctrl_flow_is_icache;
logic store_buffer_empty_verif;
// -------------- // --------------
// ISSUE <-> EX // ISSUE <-> EX
// -------------- // --------------
...@@ -453,7 +451,6 @@ module ariane import ariane_pkg::*; #( ...@@ -453,7 +451,6 @@ module ariane import ariane_pkg::*; #(
.lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit .lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit
.commit_tran_id_i ( lsu_commit_trans_id ), // from commit .commit_tran_id_i ( lsu_commit_trans_id ), // from commit
.no_st_pending_o ( no_st_pending_ex ), .no_st_pending_o ( no_st_pending_ex ),
.store_buffer_empty_o ( store_buffer_empty_verif ),
// FPU // FPU
.fpu_ready_o ( fpu_ready_ex_id ), .fpu_ready_o ( fpu_ready_ex_id ),
.fpu_valid_i ( fpu_valid_id_ex ), .fpu_valid_i ( fpu_valid_id_ex ),
...@@ -673,9 +670,6 @@ module ariane import ariane_pkg::*; #( ...@@ -673,9 +670,6 @@ module ariane import ariane_pkg::*; #(
// I$ // I$
.icache_miss_i (icache_miss_cache_perf), .icache_miss_i (icache_miss_cache_perf),
// D$
.dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty),
// IF // IF
.if_has_mem_access_i (has_mem_access_if_verif), .if_has_mem_access_i (has_mem_access_if_verif),
.if_has_cf_i (has_ctrl_flow_if_icache), .if_has_cf_i (has_ctrl_flow_if_icache),
...@@ -689,7 +683,7 @@ module ariane import ariane_pkg::*; #( ...@@ -689,7 +683,7 @@ module ariane import ariane_pkg::*; #(
.is_has_cf_i (has_ctrl_flow_is_icache), .is_has_cf_i (has_ctrl_flow_is_icache),
// LSU // LSU
.no_st_pending_commit_i (store_buffer_empty_verif), .no_st_pending_commit_i (no_st_pending_ex),
// CO // CO
.commit_instr_i (commit_instr_id_commit), .commit_instr_i (commit_instr_id_commit),
......
...@@ -71,7 +71,6 @@ module ex_stage import ariane_pkg::*; #( ...@@ -71,7 +71,6 @@ module ex_stage import ariane_pkg::*; #(
output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request
input logic [TRANS_ID_BITS-1:0] commit_tran_id_i, input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
output logic no_st_pending_o, output logic no_st_pending_o,
output logic store_buffer_empty_o,
input logic amo_valid_commit_i, input logic amo_valid_commit_i,
// FPU // FPU
output logic fpu_ready_o, // FU is ready output logic fpu_ready_o, // FU is ready
...@@ -278,7 +277,6 @@ module ex_stage import ariane_pkg::*; #( ...@@ -278,7 +277,6 @@ module ex_stage import ariane_pkg::*; #(
.rst_ni, .rst_ni,
.flush_i, .flush_i,
.no_st_pending_o, .no_st_pending_o,
.store_buffer_empty_o,
.fu_data_i ( lsu_data ), .fu_data_i ( lsu_data ),
.lsu_ready_o, .lsu_ready_o,
.lsu_valid_i, .lsu_valid_i,
......
...@@ -21,7 +21,6 @@ module load_store_unit import ariane_pkg::*; #( ...@@ -21,7 +21,6 @@ module load_store_unit import ariane_pkg::*; #(
input logic rst_ni, input logic rst_ni,
input logic flush_i, input logic flush_i,
output logic no_st_pending_o, output logic no_st_pending_o,
output logic store_buffer_empty_o,
input logic amo_valid_commit_i, input logic amo_valid_commit_i,
input fu_data_t fu_data_i, input fu_data_t fu_data_i,
...@@ -197,9 +196,9 @@ module load_store_unit import ariane_pkg::*; #( ...@@ -197,9 +196,9 @@ module load_store_unit import ariane_pkg::*; #(
end end
endgenerate endgenerate
logic store_buffer_empty;
assign store_buffer_empty_o = store_buffer_empty;
logic store_buffer_empty;
// ------------------ // ------------------
// Store Unit // Store Unit
// ------------------ // ------------------
......
...@@ -9,9 +9,6 @@ module verifier #( ...@@ -9,9 +9,6 @@ module verifier #(
// I$ // I$
input logic icache_miss_i, input logic icache_miss_i,
// D$
input logic dcache_wbuffer_empty_i,
// Frontend // Frontend
input logic if_has_mem_access_i, input logic if_has_mem_access_i,
input logic if_has_cf_i, input logic if_has_cf_i,
...@@ -38,7 +35,7 @@ module verifier #( ...@@ -38,7 +35,7 @@ module verifier #(
// Bus accesses (I$ misses and memory instructions in the pipeline) // Bus accesses (I$ misses and memory instructions in the pipeline)
logic has_mem_access; logic has_mem_access;
assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | ~no_st_pending_commit_i | ~dcache_wbuffer_empty_i; assign has_mem_access = if_has_mem_access_i | id_has_mem_access_i | is_has_mem_access_i | (~no_st_pending_commit_i);
// assign should_lock_icache_o = has_mem_access & icache_miss_i; // assign should_lock_icache_o = has_mem_access & icache_miss_i;
assign should_lock_icache_o = has_mem_access | if_has_cf_i | id_has_cf_i | is_has_cf_i; assign should_lock_icache_o = has_mem_access | if_has_cf_i | id_has_cf_i | is_has_cf_i;
......
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