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Commit 65c78308 authored by Alban Gruin's avatar Alban Gruin
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Add a destructor to dump some CSRs at the end of a bench

parent b01fc354
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...@@ -130,7 +130,7 @@ $(1): build/artifacts/$(1).D ...@@ -130,7 +130,7 @@ $(1): build/artifacts/$(1).D
$(1): build/artifacts/$(1).hex $(1): build/artifacts/$(1).hex
$(1): build/artifacts/$(1).bin $(1): build/artifacts/$(1).bin
$(1): build/mem/$(1).mem $(1): build/mem/$(1).mem
build/artifacts/$(1).riscv: build/libcva6.a $$($(1)_OBJ_FILES) build/artifacts/$(1).riscv: build/libcva6.a build/dtor.o $$($(1)_OBJ_FILES)
$$(DIR_GUARD) $$(DIR_GUARD)
@echo " LD $$@" @echo " LD $$@"
@$$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS) @$$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS)
......
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#define READCSR(_t, counter) \
asm volatile("csrr %0, " # counter : "=r" (_t))
static void __attribute__((destructor)) dtor(void) {
uint32_t brpending, mempending, lsu, imiss;
READCSR(brpending, 0xB11);
READCSR(mempending, 0xB12);
READCSR(lsu, 0xB13);
READCSR(imiss, 0xB14);
printf("==== dtor ====\n"
"brpending: %ld; mempending: %ld; lsu: %ld; imiss: %ld\n"
"==== end of dtor ====\n",
brpending, mempending, lsu, imiss);
}
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