Skip to content
Snippets Groups Projects
Commit 7794673d authored by sjthales's avatar sjthales
Browse files

updating to into account serial number of HS2 cable

parent 52d9c006
No related branches found
No related tags found
No related merge requests found
......@@ -288,7 +288,7 @@ cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga get_hs2_id
cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
......@@ -305,6 +305,11 @@ program_cva6_fpga:
@echo "[FPGA] Program FPGA"
cd fpga && make program_cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
get_hs2_sn:
@echo "[FPGA] Get HS2 serial number"
cd fpga && make get_hs2_sn
clean:
rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
......
......@@ -230,6 +230,23 @@ This platform integrates a CV32A6 processor, a JTAG interface to run and debug s
Below are described steps to run Coremark application on CV32A6 FPGA platform, steps are the same for Dhrystone application and other software applications.
The JTAG-HS2 programming cable is initially a cable that allows programming of Xilinx FPGAs (bitstream loading) from a host PC.
In our case, we use this cable to program software applications on the CV32A6 instantiated in the FPGA through a PMOD connector.
We do not use the HS2 Cable in its original function therfore there is a preliminary step which consists in retrieving the serial number of the HS2 cable.
To do this, connect the HS2 cable to the host PC (Zybo Z7-20 board must be disconnected from the host PC) and run the following command:
```
make get_hs2_sn
```
you should see:
```
...............
###############################
# TARGEt: localhost:3121/xilinx_tcf/Digilent/<**HS2's serial number**>
###############################
......................
```
Replace the **HS2's serial number** in `fpga/openocd_digilent_hs2.cfg` file by the serial number of your HS2 cable.
## Get started with Coremark application
1. First, make sure the Digilent **JTAG-HS2 debug adapter** is properly connected to the **PMOD JE** connector and that the USBUART adapter is properly connected to the **PMOD JB** connector of the Zybo Z7-20 board.
......
......@@ -63,6 +63,11 @@ else
$(VIVADO) -source scripts/program_cva6_fpga.tcl
endif
get_hs2_sn:
$(VIVADO) -mode batch -source scripts/get_hs2_sn.tcl
$(ips): %.xci :
mkdir -p $(work-dir)
......
open_hw_manager
connect_hw_server
foreach TARGET [get_hw_targets] {
puts "###############################"
puts "# TARGET: $TARGET"
puts "###############################"
}
open_hw_manager
connect_hw_server
current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/210249A85F9B"}]
current_hw_target [get_hw_targets -filter {NAME!~"localhost:3121/xilinx_tcf/Digilent/<HS2's serial number>"}]
open_hw_target
set_property PROGRAM.FILE {cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit} [get_hw_devices xc7z020_1]
current_hw_device [get_hw_devices xc7z020_1]
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment