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Commit acf7dc6a authored by sjthales's avatar sjthales
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modification student contest

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# Copyright (c) 2020 Thales.
#
# Copyright and related rights are licensed under the Apache
# License, Version 2.0 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# https://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# Author: Florian Zaruba, ETH Zurich # Author: Florian Zaruba, ETH Zurich
# Date: 03/19/2017 # Date: 03/19/2017
#
# Additional contributions by:
# Sebastien Jacq - sjthales on github.com
#
# Description: Makefile for linting and testing Ariane. # Description: Makefile for linting and testing Ariane.
#
# =========================================================================== #
# Revisions :
# Date Version Author Description
# 2020-10-06 0.1 S.Jacq modification for CVA6 softcore
# =========================================================================== #
# questa library # questa library
library ?= work library ?= work
...@@ -11,13 +32,13 @@ dpi-library ?= work-dpi ...@@ -11,13 +32,13 @@ dpi-library ?= work-dpi
# Top level module to compile # Top level module to compile
top_level ?= ariane_tb top_level ?= ariane_tb
# Maximum amount of cycles for a successful simulation run # Maximum amount of cycles for a successful simulation run
max_cycles ?= 10000000 max_cycles ?= 1000000000
# Test case to run # Test case to run
test_case ?= core_test test_case ?= core_test
# QuestaSim Version # QuestaSim Version
questa_version ?= ${QUESTASIM_VERSION} questa_version ?= ${QUESTASIM_VERSION}
# verilator version # verilator version
verilator ?= verilator #verilator ?= verilator
# traget option # traget option
target-options ?= target-options ?=
# additional definess # additional definess
...@@ -27,46 +48,25 @@ test-location ?= output/test ...@@ -27,46 +48,25 @@ test-location ?= output/test
# set to either nothing or -log # set to either nothing or -log
torture-logs := torture-logs :=
# custom elf bin to run with sim or sim-verilator # custom elf bin to run with sim or sim-verilator
elf-bin ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv elf-bin ?= sw/app/benchmarks/coremark.riscv
# board name for bitstream generation. Currently supported: kc705, genesys2
BOARD ?= genesys2 # Application to simulate
APP ?= coremark
# root path # root path
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path)) root-dir := $(dir $(mkfile_path))
support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') &> /dev/null; echo $$?) # software application path
ifeq ($(support_verilator_4), 0) app_path := $(root-dir)/sw/app
verilator_threads := 2
endif
ifndef RISCV
$(error RISCV not set - please point your RISCV variable to your RISCV installation)
endif
# setting additional xilinx board parameters for the selected board # board name for bitstream generation.
ifeq ($(BOARD), genesys2) BOARD := zybo-z7-20
XILINX_PART := xc7k325tffg900-2 XILINX_PART := xc7z020clg400-1
XILINX_BOARD := digilentinc.com:genesys2:part0:1.1 XILINX_BOARD := digilentinc.com:zybo-z7-20:part0:1.0
CLK_PERIOD_NS := 20 CLK_PERIOD_NS := 25
else ifeq ($(BOARD), kc705) BATCH_MODE ?= 1
XILINX_PART := xc7k325tffg900-2
XILINX_BOARD := xilinx.com:kc705:part0:1.5
CLK_PERIOD_NS := 20
else ifeq ($(BOARD), vc707)
XILINX_PART := xc7vx485tffg1761-2
XILINX_BOARD := xilinx.com:vc707:part0:1.3
CLK_PERIOD_NS := 20
else
$(error Unknown board - please specify a supported FPGA board)
endif
# spike tandem verification
ifdef spike-tandem
compile_flag += -define SPIKE_TANDEM
ifndef preload
$(error Tandem verification requires preloading)
endif
endif
# Sources # Sources
# Package files -> compile first # Package files -> compile first
...@@ -93,9 +93,6 @@ util := include/instr_tracer_pkg.sv \ ...@@ -93,9 +93,6 @@ util := include/instr_tracer_pkg.sv \
tb/common/mock_uart.sv \ tb/common/mock_uart.sv \
src/util/sram.sv src/util/sram.sv
ifdef spike-tandem
util += tb/common/spike.sv
endif
util := $(addprefix $(root-dir), $(util)) util := $(addprefix $(root-dir), $(util))
# Test packages # Test packages
...@@ -105,28 +102,13 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \ ...@@ -105,28 +102,13 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
# DPI # DPI
dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc)) dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
# filter spike stuff if tandem is not activated
ifndef spike-tandem
dpi := $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi))
endif
# filter dromajo stuff if dromajo is not activated
ifndef DROMAJO
dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
endif
dpi_hdr := $(wildcard tb/dpi/*.h) dpi_hdr := $(wildcard tb/dpi/*.h)
dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr)) dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
CFLAGS := -I$(QUESTASIM_HOME)/include \ CFLAGS := -I$(QUESTASIM_HOME)/include \
-I$(RISCV)/include \ -I$(RISCV)/include \
$(if $(DROMAJO), -I../tb/dromajo/src,) \
-std=c++11 -I../tb/dpi -std=c++11 -I../tb/dpi
ifdef spike-tandem
CFLAGS += -Itb/riscv-isa-sim/install/include/spike
endif
# this list contains the standalone components # this list contains the standalone components
src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \ $(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \
...@@ -214,20 +196,12 @@ fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildc ...@@ -214,20 +196,12 @@ fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildc
fpga_src := $(addprefix $(root-dir), $(fpga_src)) fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches # look for testbenches
tbs := tb/ariane_tb.sv tb/ariane_testharness.sv tbs := tb/jtag_pkg.sv tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI) # RISCV asm tests and benchmark setup (used for CI)
# there is a definesd test-list with selected CI tests # there is a definesd test-list with selected CI tests
riscv-test-dir := tmp/riscv-tests/build/isa/ riscv-test-dir := tmp/riscv-tests/build/isa/
riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
riscv-asm-tests-list := ci/riscv-asm-tests.list
riscv-amo-tests-list := ci/riscv-amo-tests.list
riscv-mul-tests-list := ci/riscv-mul-tests.list
riscv-fp-tests-list := ci/riscv-fp-tests.list
riscv-benchmarks-list := ci/riscv-benchmarks.list riscv-benchmarks-list := ci/riscv-benchmarks.list
riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list) | cut -b 1-)
riscv-amo-tests := $(shell xargs printf '\n%s' < $(riscv-amo-tests-list) | cut -b 1-)
riscv-mul-tests := $(shell xargs printf '\n%s' < $(riscv-mul-tests-list) | cut -b 1-)
riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list) | cut -b 1-)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-) riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# Search here for include files (e.g.: non-standalone components) # Search here for include files (e.g.: non-standalone components)
...@@ -242,39 +216,19 @@ compile_flag_vhd += -64 -nologo -quiet -2008 ...@@ -242,39 +216,19 @@ compile_flag_vhd += -64 -nologo -quiet -2008
# +incdir+ works for Verilator and QuestaSim # +incdir+ works for Verilator and QuestaSim
list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir)) list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
# RISCV torture setup
riscv-torture-dir := tmp/riscv-torture
# old java flags -Xmx1G -Xss8M -XX:MaxPermSize=128M
# -XshowSettings -Xdiag
riscv-torture-bin := java -jar sbt-launch.jar
# if defined, calls the questa targets in batch mode # if defined, calls the questa targets in batch mode
ifdef batch-mode ifdef batch-mode
questa-flags += -c questa-flags += -c
questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" questa-cmd := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
questa-cmd += -do " log -r /*; run -all;" questa-cmd += -do " run -all;"
else else
questa-cmd := -do " log -r /*; run -all;" questa-cmd := -do " run -all;"
endif
# we want to preload the memories
ifdef preload
questa-cmd += +PRELOAD=$(preload)
elf-bin = none
endif
ifdef spike-tandem
questa-cmd += -gblso tb/riscv-isa-sim/install/lib/libriscv.so
endif endif
# remote bitbang is enabled
ifdef rbb
questa-cmd += +jtag_rbb_enable=1
else
questa-cmd += +jtag_rbb_enable=0
endif
# Build the TB and module using QuestaSim # Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so build: $(library) $(library)/.build-srcs $(library)/.build-tb
# Optimize top level # Optimize top level
vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis vopt$(questa_version) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
...@@ -290,7 +244,7 @@ $(library)/.build-srcs: $(util) $(library) ...@@ -290,7 +244,7 @@ $(library)/.build-srcs: $(util) $(library)
touch $(library)/.build-srcs touch $(library)/.build-srcs
# build TBs # build TBs
$(library)/.build-tb: $(dpi) $(library)/.build-tb:
# Compile top level # Compile top level
vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library) vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library)
touch $(library)/.build-tb touch $(library)/.build-tb
...@@ -298,257 +252,24 @@ $(library)/.build-tb: $(dpi) ...@@ -298,257 +252,24 @@ $(library)/.build-tb: $(dpi)
$(library): $(library):
vlib${questa_version} $(library) vlib${questa_version} $(library)
# compile DPIs
$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
mkdir -p $(dpi-library)
$(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
$(dpi-library)/ariane_dpi.so: $(dpi)
mkdir -p $(dpi-library)
# Compile C-code and generate .so file
$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr
# single test runs on Questa can be started by calling make <testname>, e.g. make towers.riscv # target used to run simulation, make sim APP=<software application to run on CVA6>
# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
# if you want to run in batch mode, use make <testname> batch-mode=1 # if you want to run in batch mode, use make <testname> batch-mode=1
# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary sim: build benchmark
sim: build echo $(riscv-benchmarks)
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \ vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \ $(uvm-flags) $(QUESTASIM_FLAGS) \
${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) | tee sim.log ${top_level}_optimized +permissive-off +binary_mem=$(app_path)/$(APP).mem | tee sim.log
$(riscv-asm-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
$(riscv-amo-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-amo-tests-$@.log
$(riscv-mul-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-mul-tests-$@.log
$(riscv-fp-tests): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-fp-tests-$@.log
$(riscv-benchmarks): build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized $(QUESTASIM_FLAGS) +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
# can use -jX to run ci tests in parallel using X processes
run-asm-tests: $(riscv-asm-tests)
$(MAKE) check-asm-tests
run-amo-tests: $(riscv-amo-tests)
$(MAKE) check-amo-tests
run-mul-tests: $(riscv-mul-tests)
$(MAKE) check-mul-tests
run-fp-tests: $(riscv-fp-tests)
$(MAKE) check-fp-tests
check-asm-tests:
ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
check-amo-tests:
ci/check-tests.sh tmp/riscv-amo-tests- $(shell wc -l $(riscv-amo-tests-list) | awk -F " " '{ print $1 }')
check-mul-tests:
ci/check-tests.sh tmp/riscv-mul-tests- $(shell wc -l $(riscv-mul-tests-list) | awk -F " " '{ print $1 }')
check-fp-tests:
ci/check-tests.sh tmp/riscv-fp-tests- $(shell wc -l $(riscv-fp-tests-list) | awk -F " " '{ print $1 }')
# can use -jX to run ci tests in parallel using X processes
run-benchmarks: $(riscv-benchmarks) run-benchmarks: $(riscv-benchmarks)
$(MAKE) check-benchmarks $(MAKE) check-benchmarks
check-benchmarks: check-benchmarks:
ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }') ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
# verilator-specific benchmark:
verilate_command := $(verilator) \ cd sw/app && make $(APP).mem
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
+define+$(defines) \
src/util/sram.sv \
tb/common/mock_uart.sv \
+incdir+src/axi_node \
$(if $(verilator_threads), --threads $(verilator_threads)) \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
-Wno-PINCONNECTEMPTY \
-Wno-ASSIGNDLY \
-Wno-DECLFILENAME \
-Wno-UNUSED \
-Wno-UNOPTFLAT \
-Wno-BLKANDNBLK \
-Wno-style \
$(if $(DROMAJO), -DDROMAJO=1,) \
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
$(if $(DEBUG),--trace --trace-structs,) \
-LDFLAGS "-L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../tb/dromajo/src -ldromajo_cosim,) -lpthread" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,)" -Wall --cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--Mdir $(ver-library) -O3 \
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc $(if $(DROMAJO), tb/dpi/dromajo_cosim_dpi.cc,)
dromajo:
cd ./tb/dromajo/src && make
run-dromajo-verilator:
$(if $(BIN), $(MAKE) checkpoint_dromajo, $(error "Please provide absolute path to the binary. Usage: make run_dromajo BIN=/absolute/path/to/binary"))
checkpoint_dromajo:
cd ./tb/dromajo/run/checkpoints/ && \
rm -rf $(notdir $(BIN)) && mkdir $(notdir $(BIN)) && cd $(notdir $(BIN)) && \
cp $(BIN) . && \
echo -e "\
{\n\
\"version\":1,\n\
\"machine\":\"riscv64\",\n\
\"memory_size\":256,\n\
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"memory_base_addr\":0x80000000,\n\
\"missing_csrs\": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs\n\
0x327, 0x328, 0x329, 0x32a,\n\
0x32b, 0x32c, 0x32d, 0x32e,\n\
0x32f, 0x330, 0x331, 0x332,\n\
0x333, 0x334, 0x335, 0x336,\n\
0x337, 0x338, 0x339, 0x33a,\n\
0x33b, 0x33c, 0x33d, 0x33e,\n\
0x33f,\n\
0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs\n\
0x3b0, 0x3b1, 0x3b2, 0x3b3,\n\
0x3b4, 0x3b5, 0x3b6, 0x3b7,\n\
0x3b8, 0x3b9, 0x3ba, 0x3bb,\n\
0x3bc, 0x3bd, 0x3be, 0x3bf,\n\
0x320], //mcountinhibit\n\
\"maxinsns\": 100,\n\
\"clint_base_addr\": 0x02000000,\n\
\"clint_size\": 0xC0000,\n\
\"plic_base_addr\": 0x0C000000,\n\
\"plic_size\": 0x3FFFFFF,\n\
\"uart_base_addr\": 0x10000000,\n\
\"uart_size\": 0x1000\n\
}" > "$(notdir $(BIN))_boot.cfg" && \
echo -e "\
{\n\
\"version\":1,\n\
\"machine\":\"riscv64\",\n\
\"memory_size\":256,\n\
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"load\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"skip_commit\": [0x73, 0x9002, 0x100073],\n\
\"memory_base_addr\":0x80000000,\n\
\"clint_base_addr\": 0x02000000,\n\
\"clint_size\": 0xC0000,\n\
\"plic_base_addr\": 0x0C000000,\n\
\"plic_size\": 0x3FFFFFF,\n\
\"uart_base_addr\": 0x10000000,\n\
\"uart_size\": 0x1000\n\
}" > "$(notdir $(BIN)).cfg" && \
../../../src/dromajo --save=$(notdir $(BIN)) --save_format=1 ./$(notdir $(BIN))_boot.cfg && \
cd ../../../../../ && \
./work-ver/Variane_testharness +checkpoint=$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))
# User Verilator, at some point in the future this will be auto-generated
verilate: $(if $(DROMAJO), dromajo,)
@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
$(verilate_command)
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk
sim-verilator: verilate
$(ver-library)/Variane_testharness $(elf-bin)
$(addsuffix -verilator,$(riscv-asm-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-amo-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-mul-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-fp-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
run-all-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(run-mul-verilator)) $(addsuffix -verilator, $(riscv-fp-tests))
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
run-amo-verilator: $(addsuffix -verilator, $(riscv-amo-tests))
run-mul-verilator: $(addsuffix -verilator, $(riscv-mul-tests))
run-fp-verilator: $(addsuffix -verilator, $(riscv-fp-tests))
run-fp-d-verilator: $(addsuffix -verilator, $(filter rv64ud%, $(riscv-fp-tests)))
run-fp-f-verilator: $(addsuffix -verilator, $(filter rv64uf%, $(riscv-fp-tests)))
run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
# torture-specific
torture-gen:
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
torture-itest:
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
torture-rtest: build
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=$(test-location)" > call.sh && chmod +x call.sh
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a $(test-location).S' | tee $(test-location).log
make check-torture test-location=$(test-location)
torture-dummy: build
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh
torture-rnight: build
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture$(torture-logs) batch-mode=1 defines=$(defines) test-location=\$${@: -1}" > call.sh && chmod +x call.sh
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'overnight/run -r ./call.sh -g none' | tee output/overnight.log
$(MAKE) check-torture
torture-rtest-verilator: verilate
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && $(MAKE) run-torture-verilator batch-mode=1 defines=$(defines)" > call.sh && chmod +x call.sh
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
$(MAKE) check-torture
run-torture: build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
run-torture-log: build
vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles)+UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) +jtag_rbb_enable=0 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off +signature=$(riscv-torture-dir)/$(test-location).rtlsim.sig ++$(riscv-torture-dir)/$(test-location) ++$(target-options)
cp vsim.wlf $(riscv-torture-dir)/$(test-location).wlf
cp trace_hart_0000.log $(riscv-torture-dir)/$(test-location).trace
cp trace_hart_0000_commit.log $(riscv-torture-dir)/$(test-location).commit
cp transcript $(riscv-torture-dir)/$(test-location).transcript
run-torture-verilator: verilate
$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
check-torture:
grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv) fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv) fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
...@@ -557,30 +278,27 @@ fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv) ...@@ -557,30 +278,27 @@ fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv) fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv) fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) # target rused to run synthesis and place and route in out of context mode
@echo "[FPGA] Generate sources" # make cva6_ooc CLK_PERIOD_NS=<period of the CVA6 architecture>
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo "Generate sources for synthesis"
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
@echo "[FPGA] Generate Bitstream" cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
cd fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
.PHONY: fpga
build-spike: .PHONY: cva6_ooc
cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install
clean: clean:
rm -rf $(riscv-torture-dir)/output/test* rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/ rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
cd sw/app && make clean
cd fpga && make clean
.PHONY: .PHONY:
build sim sim-verilate clean \ build sim benchmark clean \
$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \ $(riscv-benchmarks) \
$(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \ check-benchmarks
check-benchmarks check-asm-tests \
torture-gen torture-itest torture-rtest \
run-torture run-torture-verilator check-torture check-torture-verilator
This diff is collapsed.
VIVADO ?= vivado # Copyright (c) 2020 Thales.
VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl #
# Copyright and related rights are licensed under the Solderpad
work-dir := work-fpga # License, Version 2.0 (the "License"); you may not use this file except in
bit := $(work-dir)/ariane_xilinx.bit # compliance with the License. You may obtain a copy of the License at
mcs := $(work-dir)/ariane_xilinx.mcs # http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
ip-dir := xilinx # or agreed to in writing, software, hardware and materials distributed under
ips := xlnx_axi_clock_converter.xci \ # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
xlnx_axi_dwidth_converter.xci \ # CONDITIONS OF ANY KIND, either express or implied. See the License for the
xlnx_axi_quad_spi.xci \ # specific language governing permissions and limitations under the License.
xlnx_axi_gpio.xci \ #
xlnx_clk_gen.xci \ # Author: Sebastien Jacq - sjthales on github.com
xlnx_mig_7_ddr3.xci
#
ips := $(addprefix $(work-dir)/, $(ips)) # Additional contributions by:
ips-target := $(join $(addsuffix /ip/, $(addprefix $(ip-dir)/, $(basename $(ips)))), $(ips)) #
#
all: $(mcs) # script Name: Hardware architecture Makefile
# Project Name: CVA6 softcore
# Language: Makefile
#
# Description: Makefile to synthesize/place and route CVA6 architecture
#
# =========================================================================== #
# Revisions :
# Date Version Author Description
# 2020-10-06 0.1 S.Jacq Created
# =========================================================================== #
# Generate mcs from bitstream VIVADO ?= vivado
$(mcs): $(bit)
$(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^
$(bit): $(ips)
mkdir -p $(work-dir)
$(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl
cp ariane.runs/impl_1/ariane_xilinx* ./$(work-dir)
$(ips): %.xci : all: $(cva6_ooc)
mkdir -p $(work-dir)
@echo Generating $(@F)
@cd $(ip-dir)/$(basename $(@F)) && make clean && make
@cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@
mcs: $(mcs) cva6_ooc:
ifeq ($(BATCH_MODE), 1)
$(VIVADO) -mode batch -source scripts/run_cva6_ooc.tcl
else
$(VIVADO) -source scripts/run_cva6_ooc.tcl
endif
program:
$(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl
clean: clean:
rm -rf *.log *.jou *.str *.mif *.xpr $(work-dir) ariane.cache ariane.hw ariane.ip_user_files rm -rf *.log \
*.jou \
*.str \
*.mif \
*.xpr \
cva6_ooc.cache \
cva6_ooc.hw \
cva6_ooc.ip_user_files \
cva6_ooc.sim \
cva6_ooc.runs \
cva6_ooc.hbs \
.Xil \
reports_cva6_ooc_synth \
reports_cva6_ooc_impl
.PHONY: .PHONY:
clean clean
adapter_khz 1000
interface ftdi
ftdi_vid_pid 0x0403 0x6010
# Channel 1 is taken by Xilinx JTAG
ftdi_channel 0
# links:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
#
# Bit MPSSE FT2232 JTAG Type Description
# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
# Bit1 TDI ADBUS1 TDI Out Serial Data Out
# Bit2 TDO ADBUS2 TDO In Serial Data In
# Bit3 TMS ADBUS3 TMS Out Select Signal Out
# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
# this corresponds to the following in/out layout, with TMS initially set to 1
ftdi_layout_init 0x0018 0x001b
# we only have to specify nTRST, the others are assigned correctly by default
ftdi_layout_signal nTRST -ndata 0x0010
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba off
init
halt
echo "Ready for Remote Connections"
adapter_khz 1000
interface ftdi
ftdi_vid_pid 0x0403 0x6010
# Channel 1 is taken by Xilinx JTAG
ftdi_channel 0
# links:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
#
# Bit MPSSE FT2232 JTAG Type Description
# Bit0 TCK ADBUS0 TCK Out Clock Signal Output
# Bit1 TDI ADBUS1 TDI Out Serial Data Out
# Bit2 TDO ADBUS2 TDO In Serial Data In
# Bit3 TMS ADBUS3 TMS Out Select Signal Out
# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O
# this corresponds to the following in/out layout, with TMS initially set to 1
ftdi_layout_init 0x0018 0x001b
# we only have to specify nTRST, the others are assigned correctly by default
ftdi_layout_signal nTRST -ndata 0x0010
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba off
# Try enabling address translation (only works for newer versions)
if { [catch {riscv set_enable_virtual on} ] } {
echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
init
halt
echo "Ready for Remote Connections"
adapter_khz 1000
interface ftdi
# ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232"
ftdi_vid_pid 0x15ba 0x002b
ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
# select the HART to debug with the coreid switch
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba off
init
halt
echo "Ready for Remote Connections"
adapter_khz 1000
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a
ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
# select the HART to debug with the coreid switch
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
gdb_report_data_abort enable
gdb_report_register_access_error enable
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
# prefer to use sba for system bus access
riscv set_prefer_sba off
init
halt
echo "Ready for Remote Connections"
## Common Ariane XDCs
create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
set_input_jitter tck 1.000
# minimize routing delay
set_input_delay -clock tck -clock_fall 5 [get_ports tdi ]
set_input_delay -clock tck -clock_fall 5 [get_ports tms ]
set_output_delay -clock tck 5 [get_ports tdo ]
set_false_path -from [get_ports trst_n ]
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
# set multicycle path on reset, on the FPGA we do not care about the reset anyway
set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold
## Buttons
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports cpu_resetn]
## To use FTDI FT2232 JTAG
set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { tck }];
set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }];
## UART
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx]
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports rx]
## LEDs
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {led[4]}]
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports {led[5]}]
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports {led[6]}]
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports {led[7]}]
## Switches
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
## Fan Control
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports fan_pwm]
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
## Ethernet
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS15} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict {PACKAGE_PIN AK14 IOSTANDARD LVCMOS15} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
set_property -dict {PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
set_property -dict {PACKAGE_PIN AK11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
set_property -dict {PACKAGE_PIN AK10 IOSTANDARD LVCMOS15} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS15} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS15} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS15} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS15} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
#############################################
# Ethernet Constraints for 1Gb/s
#############################################
# Modified for 125MHz receive clock
create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
#############################################
## SD Card
#############################################
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
# Genesys 2 has a quad SPI flash
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports { tdo } ] 20
set_max_delay -from [get_ports { tms } ] 20
set_max_delay -from [get_ports { tdi } ] 20
set_max_delay -from [get_ports { trst_n } ] 20
# reset signal
set_false_path -from [get_ports { trst_n } ]
set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
## Buttons
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS15} [get_ports cpu_reset]
set_property slave_banks {32 34} [get_iobanks 33]
# on board differential clock, 200MHz
set_property PACKAGE_PIN AD12 [get_ports sys_clk_p]
set_property PACKAGE_PIN AD11 [get_ports sys_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
## To use FTDI FT2232 JTAG
# Reset Not connected because optional?
set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS33 } [get_ports { tck }];
set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { trst_n }];
set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS33 } [get_ports { tdo }];
set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS33 } [get_ports { tdi }];
set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS33 } [get_ports { tms }];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
## UART
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS25} [get_ports tx]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx]
## LEDs
# set_property -dict {PACKAGE_PIN DS4 IOSTANDARD LVCMOS25} [get_ports {led[0]}]
# set_property -dict {PACKAGE_PIN DS1 IOSTANDARD LVCMOS25} [get_ports {led[1]}]
# set_property -dict {PACKAGE_PIN DS10 IOSTANDARD LVCMOS25} [get_ports {led[2]}]
# set_property -dict {PACKAGE_PIN DS2 IOSTANDARD LVCMOS25} [get_ports {led[3]}]
# set_property -dict {PACKAGE_PIN DS3 IOSTANDARD LVCMOS25} [get_ports {led[4]}]
# set_property -dict {PACKAGE_PIN DS25 IOSTANDARD LVCMOS25} [get_ports {led[5]}]
# set_property -dict {PACKAGE_PIN DS26 IOSTANDARD LVCMOS25} [get_ports {led[6]}]
# set_property -dict {PACKAGE_PIN DS27 IOSTANDARD LVCMOS25} [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
#set_property SLEW SLOW [get_ports {led[0]}]
#set_property DRIVE 4 [get_ports {led[0]}]
#set_property LOC AB8 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
#set_property SLEW SLOW [get_ports {led[1]}]
#set_property DRIVE 4 [get_ports {led[1]}]
#set_property LOC AA8 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
#set_property SLEW SLOW [get_ports {led[2]}]
#set_property DRIVE 4 [get_ports {led[2]}]
#set_property LOC AC9 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
#set_property SLEW SLOW [get_ports {led[3]}]
#set_property DRIVE 4 [get_ports {led[3]}]
#set_property LOC AB9 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}]
#set_property SLEW SLOW [get_ports {led[4]}]
#set_property DRIVE 4 [get_ports {led[4]}]
#set_property LOC AE26 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}]
#set_property SLEW SLOW [get_ports {led[5]}]
#set_property DRIVE 4 [get_ports {led[5]}]
#set_property LOC G19 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}]
#set_property SLEW SLOW [get_ports {led[6]}]
#set_property DRIVE 4 [get_ports {led[6]}]
#set_property LOC E18 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}]
#set_property SLEW SLOW [get_ports {led[7]}]
#set_property DRIVE 4 [get_ports {led[7]}]
#set_property LOC F16 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led[0]}]
set_property SLEW SLOW [get_ports {led[0]}]
set_property DRIVE 4 [get_ports {led[0]}]
set_property LOC AE26 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led[1]}]
set_property SLEW SLOW [get_ports {led[1]}]
set_property DRIVE 4 [get_ports {led[1]}]
set_property LOC G19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led[2]}]
set_property SLEW SLOW [get_ports {led[2]}]
set_property DRIVE 4 [get_ports {led[2]}]
set_property LOC E18 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led[3]}]
set_property SLEW SLOW [get_ports {led[3]}]
set_property DRIVE 4 [get_ports {led[3]}]
set_property LOC F16 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[4]}]
#set_property SLEW SLOW [get_ports {led[4]}]
#set_property DRIVE 4 [get_ports {led[4]}]
#set_property LOC AB8 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[5]}]
#set_property SLEW SLOW [get_ports {led[5]}]
#set_property DRIVE 4 [get_ports {led[5]}]
#set_property LOC AA8 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[6]}]
#set_property SLEW SLOW [get_ports {led[6]}]
#set_property DRIVE 4 [get_ports {led[6]}]
#set_property LOC AC9 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS15 [get_ports {led[7]}]
#set_property SLEW SLOW [get_ports {led[7]}]
#set_property DRIVE 4 [get_ports {led[7]}]
#set_property LOC AB9 [get_ports {led[7]}]
## Switches
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS25} [get_ports {sw[0]}]
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports {sw[1]}]
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports {sw[2]}]
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25} [get_ports {sw[3]}]
#set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
#set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
#set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {sw[6]}]
#set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {sw[7]}]
## Fan Control
set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS25} [get_ports fan_pwm]
#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
## Ethernet
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS25} [get_ports { eth_rst_n }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
set_property -dict {PACKAGE_PIN M28 IOSTANDARD LVCMOS25} [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS25} [get_ports { eth_txctl }]; #IO_L20P_T3_33 Sch=eth_tx_en
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS25} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
set_property -dict {PACKAGE_PIN M29 IOSTANDARD LVCMOS25} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
set_property -dict {PACKAGE_PIN L28 IOSTANDARD LVCMOS25} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS25} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
#############################################
# Ethernet Constraints for 1Gb/s
#############################################
# Modified for 125MHz receive clock
create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
#############################################
## SD Card
#############################################
set_property -dict {PACKAGE_PIN AB23 IOSTANDARD LVCMOS25} [get_ports spi_clk_o]
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports spi_ss]
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVCMOS25} [get_ports spi_miso]
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports spi_mosi]
# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
# Genesys 2 has a quad SPI flash
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports { tdo } ] 20
set_max_delay -from [get_ports { tms } ] 20
set_max_delay -from [get_ports { tdi } ] 20
set_max_delay -from [get_ports { trst_n } ] 20
# reset signal
set_false_path -from [get_ports { trst_n } ]
set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
## Buttons
set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports cpu_reset]
## To use FTDI FT2232 JTAG
set_property -dict { PACKAGE_PIN AV39 IOSTANDARD LVCMOS18 } [get_ports trst];
set_property -dict { PACKAGE_PIN M32 IOSTANDARD LVCMOS18 } [get_ports tck ];
set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS18 } [get_ports tdi ];
set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS18 } [get_ports tdo ];
set_property -dict { PACKAGE_PIN U31 IOSTANDARD LVCMOS18 } [get_ports tms ];
## UART
set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports tx]
set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports rx]
## LEDs
set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports {led[3]}]
set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports {led[4]}]
set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports {led[5]}]
set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports {led[6]}]
set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports {led[7]}]
## Switches
set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports {sw[0]}]
set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports {sw[1]}]
set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports {sw[2]}]
set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports {sw[3]}]
set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports {sw[4]}]
set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports {sw[5]}]
set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports {sw[6]}]
set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports {sw[7]}]
## Fan Control
set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS18 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tac
## Ethernet
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS18} [get_ports eth_rst_n]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
set_property -dict {PACKAGE_PIN N25 IOSTANDARD LVCMOS18} [get_ports eth_txck]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports eth_txctl]; #IO_L20P_T3_33 Sch=eth_tx_en
set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS18} [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
set_property -dict {PACKAGE_PIN L27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
set_property -dict {PACKAGE_PIN M27 IOSTANDARD LVCMOS18} [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS18} [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS18} [get_ports eth_rxck]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports eth_rxctl]; #IO_L18P_T2_33 Sch=eth_rx_ctl
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
set_property -dict {PACKAGE_PIN L26 IOSTANDARD LVCMOS18} [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS18} [get_ports eth_mdc ]; #IO_L23P_T3_33 Sch=eth_mdc
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports eth_mdio]; #IO_L23N_T3_33 Sch=eth_mdio
# set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
# set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS18} [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
#############################################
# Ethernet Constraints for 1Gb/s
#############################################
# Modified for 125MHz receive clock
create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck]
set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks clk_out2_xlnx_clk_gen]
#############################################
## SD Card
#############################################
set_property -dict {PACKAGE_PIN AN30 IOSTANDARD LVCMOS18} [get_ports spi_clk_o]
set_property -dict {PACKAGE_PIN AT30 IOSTANDARD LVCMOS18} [get_ports spi_ss]
set_property -dict {PACKAGE_PIN AR30 IOSTANDARD LVCMOS18} [get_ports spi_miso]
set_property -dict {PACKAGE_PIN AP30 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
# set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS18 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
# set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS18 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
# set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
# set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
# set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
# set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS18 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
# set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS18 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
# set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS18 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~ "*sd*" }]
# Genesys 2 has a quad SPI flash
# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports tdo ] 20
set_max_delay -from [get_ports tms ] 20
set_max_delay -from [get_ports tdi ] 20
set_max_delay -from [get_ports trst ] 20
# reset signal
# set_false_path -from [get_ports { trst } ]
# set_false_path -from [get_pins i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
Source diff could not be displayed: it is too large. Options to address this: view the blob.
# Copyright 2018 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# Description: Program Genesys II
open_hw
connect_hw_server -url localhost:3121
if {$::env(BOARD) eq "genesys2"} {
open_hw_target {localhost:3121/xilinx_tcf/Digilent/200300A8CD43B}
current_hw_device [get_hw_devices xc7k325t_0]
set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7k325t_0]
program_hw_devices [get_hw_devices xc7k325t_0]
refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0]
} elseif {$::env(BOARD) eq "vc707"} {
open_hw_target {localhost:3121/xilinx_tcf/Digilent/210203A5FC70A}
current_hw_device [get_hw_devices xc7vx485t_0]
set_property PROGRAM.FILE {work-fpga/ariane_xilinx.bit} [get_hw_devices xc7vx485t_0]
program_hw_devices [get_hw_devices xc7vx485t_0]
refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0]
} else {
exit 1
}
# Copyright 2018 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
set project ariane
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-4480]} -limit 1000
\ No newline at end of file
# Copyright 2018 ETH Zurich and University of Bologna. # Copyright (c) 2020 Thales.
#
# Copyright and related rights are licensed under the Solderpad
# License, Version 2.0 (the "License"); you may not use this file except in
# compliance with the License. You may obtain a copy of the License at
# http://solderpad.org/licenses/SHL-2.0/ Unless required by applicable law
# or agreed to in writing, software, hardware and materials distributed under
# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied. See the License for the
# specific language governing permissions and limitations under the License.
#
# Author: Sebastien Jacq - sjthales on github.com
#
# Additional contributions by:
# #
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
# #
# http://www.apache.org/licenses/LICENSE-2.0 # script Name: run_cva6_ooc
# Project Name: CVA6 softcore
# Language: tcl
# #
# Unless required by applicable law or agreed to in writing, software # Description: Script to synthesize/place and route CVA6 architecture
# distributed under the License is distributed on an "AS IS" BASIS, # in out of context mode
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
# See the License for the specific language governing permissions and # =========================================================================== #
# limitations under the License. # Revisions :
# Date Version Author Description
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> # 2020-10-06 0.1 S.Jacq Created
# =========================================================================== #
# hard-coded to Genesys 2 for the moment set project cva6_ooc
if {$::env(BOARD) eq "genesys2"} { create_project $project . -force -part $::env(XILINX_PART)
add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc set_property board_part $::env(XILINX_BOARD) [current_project]
} elseif {$::env(BOARD) eq "kc705"} {
add_files -fileset constrs_1 -norecurse constraints/kc705.xdc
} elseif {$::env(BOARD) eq "vc707"} {
add_files -fileset constrs_1 -norecurse constraints/vc707.xdc # set number of threads to 8 (maximum, unfortunately)
} else { set_param general.maxThreads 8
exit 1
} set_msg_config -id {[Synth 8-5858]} -new_severity "info"
read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci set_msg_config -id {[Synth 8-4480]} -limit 1000
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
read_ip xilinx/xlnx_axi_dwidth_converter/ip/xlnx_axi_dwidth_converter.xci
read_ip xilinx/xlnx_axi_gpio/ip/xlnx_axi_gpio.xci
read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci
read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
# read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci
set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset] set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
source scripts/add_sources.tcl source scripts/add_sources.tcl
set_property top ${project}_xilinx [current_fileset] set_property top ariane [current_fileset]
if {$::env(BOARD) eq "genesys2"} { read_verilog -sv {src/zybo-z7-20.svh ../src/common_cells/include/common_cells/registers.svh}
read_verilog -sv {src/genesysii.svh ../src/common_cells/include/common_cells/registers.svh} set file "src/zybo-z7-20.svh"
set file "src/genesysii.svh" set registers "../src/common_cells/include/common_cells/registers.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
} elseif {$::env(BOARD) eq "kc705"} {
read_verilog -sv {src/kc705.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/kc705.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
} elseif {$::env(BOARD) eq "vc707"} {
read_verilog -sv {src/vc707.svh ../src/common_cells/include/common_cells/registers.svh}
set file "src/vc707.svh"
set registers "../src/common_cells/include/common_cells/registers.svh"
} else {
exit 1
}
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse constraints/$project.xdc
synth_design -rtl -name rtl_1
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
launch_runs synth_1 launch_runs synth_1
wait_on_run synth_1 wait_on_run synth_1
open_run synth_1 open_run synth_1
exec mkdir -p reports/ exec mkdir -p reports_cva6_ooc_synth/
exec rm -rf reports/* exec rm -rf reports_cva6_ooc_synth/*
check_timing -verbose -file reports/$project.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt check_timing -verbose -file reports_cva6_ooc_synth/$project.check_timing.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_ooc_synth/$project.timing_WORST_100.rpt
report_utilization -hierarchical -file reports/$project.utilization.rpt report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_ooc_synth/$project.timing.rpt
report_cdc -file reports/$project.cdc.rpt report_utilization -hierarchical -file reports_cva6_ooc_synth/$project.utilization.rpt
report_clock_interaction -file reports/$project.clock_interaction.rpt report_cdc -file reports_cva6_ooc_synth/$project.cdc.rpt
report_clock_interaction -file reports_cva6_ooc_synth/$project.clock_interaction.rpt
# set for RuntimeOptimized implementation # set for RuntimeOptimized implementation
set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
create_clock -period $::env(CLK_PERIOD_NS) -name clk_i [get_ports clk_i]
#set_property HD.CLK_SRC BUFGCTRL_X1Y2 [get_ports clk_i]
launch_runs impl_1 launch_runs impl_1
wait_on_run impl_1 wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
# output Verilog netlist + SDC for timing simulation
write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
write_verilog -force -mode timesim work-fpga/${project}_timesim.v
write_sdf -force work-fpga/${project}_timesim.sdf
# reports # reports
exec mkdir -p reports/ exec mkdir -p reports_cva6_ooc_impl/
exec rm -rf reports/* exec rm -rf reports_cva6_ooc_impl/*
check_timing -file reports/${project}.check_timing.rpt check_timing -file reports_cva6_ooc_impl/${project}.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_ooc_impl/${project}.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_ooc_impl/${project}.timing.rpt
report_utilization -hierarchical -file reports/${project}.utilization.rpt report_utilization -hierarchical -file reports_cva6_ooc_impl/${project}.utilization.rpt
# Copyright 2018 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# Description: Generate a memory configuration file from a bitstream (Genesys II only right now)
if {$argc < 2 || $argc > 4} {
puts $argc
puts {Error: Invalid number of arguments}
puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]}
exit 1
}
lassign $argv mcsfile bitfile
# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash
# https://scholar.princeton.edu/jbalkind/blog/programming-vc707-virtex-7-bpi-flash
if {$::env(BOARD) eq "genesys2"} {
write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
} elseif {$::env(BOARD) eq "vc707"} {
write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force
} else {
exit 1
}
#!/bin/bash
# genesys2
if [ -z "${BOARD}" ]; then
export BOARD="genesys2"
fi
if [ "$BOARD" = "genesys2" ]; then
echo -n "Configuring for "
echo "Genesys II"
export XILINX_PART="xc7k325tffg900-2"
export XILINX_BOARD="digilentinc.com:genesys2:part0:1.1"
export CLK_PERIOD_NS="20"
fi
if [ "$BOARD" = "kc705" ]; then
echo -n "Configuring for "
echo "Kintex kc705"
export XILINX_PART="xc7k325tffg900-2"
export XILINX_BOARD="xilinx.com:kc705:part0:1.5"
export CLK_PERIOD_NS="20"
fi
if [ "$BOARD" = "vc707" ]; then
echo -n "Configuring for "
echo "Virtex vc707"
export XILINX_PART="xc7vx485tffg1761-2"
export XILINX_BOARD="xilinx.com:vc707:part0:1.3"
export CLK_PERIOD_NS="20"
fi
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE
xlnx*/*
!xlnx*/tcl
!Makefile
!common.mk
!*.prj
\ No newline at end of file
xlnx_axi_dwidth_converter:
ip: axi_dwidth_converter
vendor: xilinx.com
config:
si_data_width: 64
si_id_width: 5
mi_data_width: 32
xlnx_axi_clock_converter:
ip: axi_clock_converter
vendor: xilinx.com
config:
width: 64
data_width: 64
id_width: 5
xlnx_axi_gpio:
ip: axi_gpio
vendor: xilinx.com
config:
c_gpio_width: 8
c_gpio2_width: 8
c_is_dual: 1
c_all_inputs_2: 1
c_interrupt_present: 0
xlnx_axi_quad_spi:
ip: axi_quad_spi
vendor: xilinx.com
config:
c_use_startup: 0
c_sck_ratio: 4
c_fifo_depth: 256
c_type_of_axi4_interface: 1
c_s_axi4_id_width: 0
xlnx_clk_gen:
ip: clk_wiz
vendor: xilinx.com
config:
prim_in_freq: 200
num_out_clks: 4
clkout2_used: true
clkout3_used: true
clkout4_used: true
clkout1_requested_out_freq: 50
clkout2_requested_out_freq: 125
clkout3_requested_out_freq: 125
clkout3_requested_phase: 90
clkout4_requested_out_freq: 50
clkin1_jitter_ps: 50
xlnx_ila:
ip: ila
vendor: xilinx.com
config:
c_num_of_probes: 8
c_probe3_width: 4
c_probe6_width: 4
c_data_depth: 16384
c_input_pipe_stages: 1
xlnx_mig_7_ddr3:
ip: mig_7series
vendor: xilinx.com
config:
xml_input_file: mig_a.prj
reset_board_interface: Custom
mig_dont_touch_param: Custom
board_mig_param: Custom
xlnx_ila:
ip: xlnx_ila
vendor: xilinx.com
config:
addr_width: 64
data_width: 64
id_width: 5
awuser_width: 1
aruser_width: 1
ruser_width: 1
wuser_width: 1
buser_width: 1
max_aw_waits: 1024
max_ar_waits: 1024
max_w_waits: 1024
max_r_waits: 1024
max_b_waits: 1024
max_continuous_wtransfers_waits: 1024
max_wlast_to_awvalid_waits: 1024
max_write_to_bvalid_waits: 1024
max_continuous_rtransfers_waits: 1024
\ No newline at end of file
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