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Commit ad223cfd authored by Florian Zaruba's avatar Florian Zaruba
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Clean-up naming to distinguish OP from GP Ariane (#193)

* Clean-up naming to distinguish  OP from GP Ariane

* Rename wb to wt in hidden CI files

* Fix verilator install script
parent e0a71ea0
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with 219 additions and 263 deletions
...@@ -29,7 +29,7 @@ variables: ...@@ -29,7 +29,7 @@ variables:
stages: stages:
- build - build
- standard - standard
- serpent - wb
################################### ###################################
# prepare # prepare
...@@ -52,28 +52,28 @@ build: ...@@ -52,28 +52,28 @@ build:
asm-quest: asm-quest:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-asm-tests batch-mode=1 - make -j${NUM_JOBS} run-asm-tests batch-mode=1 defines=WB_DCACHE
dependencies: dependencies:
- build - build
amo-quest: amo-quest:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-amo-tests batch-mode=1 - make -j${NUM_JOBS} run-amo-tests batch-mode=1 defines=WB_DCACHE
dependencies: dependencies:
- build - build
fp-quest: fp-quest:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-fp-tests batch-mode=1 - make -j${NUM_JOBS} run-fp-tests batch-mode=1 defines=WB_DCACHE
dependencies: dependencies:
- build - build
bench-quest: bench-quest:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-benchmarks batch-mode=1 - make -j${NUM_JOBS} run-benchmarks batch-mode=1 defines=WB_DCACHE
dependencies: dependencies:
- build - build
...@@ -81,7 +81,7 @@ bench-quest: ...@@ -81,7 +81,7 @@ bench-quest:
asm1-ver: asm1-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-asm-tests1-verilator - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
...@@ -89,7 +89,7 @@ asm1-ver: ...@@ -89,7 +89,7 @@ asm1-ver:
asm2-ver: asm2-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-asm-tests2-verilator - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
...@@ -97,7 +97,7 @@ asm2-ver: ...@@ -97,7 +97,7 @@ asm2-ver:
mul-ver: mul-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-mul-verilator - make -j${NUM_JOBS} run-mul-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
...@@ -105,7 +105,7 @@ mul-ver: ...@@ -105,7 +105,7 @@ mul-ver:
amo-ver: amo-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-amo-verilator - make -j${NUM_JOBS} run-amo-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
...@@ -113,21 +113,21 @@ amo-ver: ...@@ -113,21 +113,21 @@ amo-ver:
fp-ver: fp-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-fp-verilator - make -j${NUM_JOBS} run-fp-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
bench-ver: bench-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-benchmarks-verilator - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
dependencies: dependencies:
- build - build
bench-ver: bench-ver:
stage: standard stage: standard
script: script:
- make -j${NUM_JOBS} run-benchmarks-verilator - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
...@@ -149,96 +149,96 @@ serdiv-quest: ...@@ -149,96 +149,96 @@ serdiv-quest:
- build - build
################################### ###################################
# tests with serpent cache system # tests with write-through cache system
s-asm-quest: s-asm-quest:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-asm-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 - make -j${NUM_JOBS} run-asm-tests defines=WT_DCACHE batch-mode=1
dependencies: dependencies:
- build - build
# atomics # atomics
s-amo-quest: s-amo-quest:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-amo-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 - make -j${NUM_JOBS} run-amo-tests defines=WT_DCACHE batch-mode=1
dependencies: dependencies:
- build - build
# floating point # floating point
s-fp-quest: s-fp-quest:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-fp-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 - make -j${NUM_JOBS} run-fp-tests defines=WT_DCACHE batch-mode=1
dependencies: dependencies:
- build - build
s-bench-quest: s-bench-quest:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-benchmarks defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 - make -j${NUM_JOBS} run-benchmarks defines=WT_DCACHE batch-mode=1
dependencies: dependencies:
- build - build
# rv64ui-p-* tests # rv64ui-p-* tests
s-asm1-ver: s-asm1-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
# rv64ui-v-* tests # rv64ui-v-* tests
s-asm2-ver: s-asm2-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
# rv64um-*-* tests # rv64um-*-* tests
mul-ver: mul-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-mul-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-mul-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
# atomics # atomics
amo-ver: amo-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-amo-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-amo-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
# floating point # floating point
s-fp-ver: s-fp-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-fp-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-fp-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
s-bench-ver: s-bench-ver:
stage: serpent stage: write-through
script: script:
- make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
dependencies: dependencies:
- build - build
s-icache-quest: s-icache-quest:
stage: serpent stage: write-through
script: script:
- cd tb/tb_serpent_icache/ - cd tb/tb_wt_icache/
- make simc - make simc
- "grep 'CI: PASSED' summary.rep" - "grep 'CI: PASSED' summary.rep"
s-dcache-quest: s-dcache-quest:
stage: serpent stage: write-through
script: script:
- cd tb/tb_serpent_dcache/ - cd tb/tb_wT_dcache/
- make simc - make simc
- "grep 'CI: PASSED' RD0_summary.rep" - "grep 'CI: PASSED' RD0_summary.rep"
- "grep 'CI: PASSED' RD1_summary.rep" - "grep 'CI: PASSED' RD1_summary.rep"
...@@ -247,9 +247,9 @@ s-dcache-quest: ...@@ -247,9 +247,9 @@ s-dcache-quest:
- build - build
# s-torture: # s-torture:
# stage: serpent # stage: write-through
# script: # script:
# - make torture-rtest defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1 # - make torture-rtest defines=WT_DCACHE batch-mode=1
# - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS # - make torture-rtest-verilator defines=WT_DCACHE
# dependencies: # dependencies:
# - build # - build
...@@ -81,34 +81,34 @@ jobs: ...@@ -81,34 +81,34 @@ jobs:
- ci/install-dtc.sh - ci/install-dtc.sh
- ci/install-spike.sh - ci/install-spike.sh
- stage: test - stage: test
name: run riscv benchmarks name: run riscv benchmarks (Write-Back Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-benchmarks-verilator - make -j${NUM_JOBS} run-benchmarks-verilator defines=WB_DCACHE
# rv64ui-p-* tests # rv64ui-p-* tests
- stage: test - stage: test
name: run asm tests1 name: run asm tests1 (Write-Back Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests1-verilator - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WB_DCACHE
# rv64ui-v-* tests # rv64ui-v-* tests
- stage: test - stage: test
name: run asm tests2 name: run asm tests2 (Write-Back Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WB_DCACHE
# rv64um-*-* tests # rv64um-*-* tests
- stage: test - stage: test
name: run mul tests name: run mul tests (Write-Back Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-mul-verilator - make -j${NUM_JOBS} run-mul-verilator defines=WB_DCACHE
# amo tests # amo tests
- stage: test - stage: test
name: run amo tests name: run amo tests (Write-Back Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-amo-verilator - make -j${NUM_JOBS} run-amo-verilator defines=WB_DCACHE
- stage: test - stage: test
name: run torture name: run torture
script: script:
...@@ -118,37 +118,35 @@ jobs: ...@@ -118,37 +118,35 @@ jobs:
- make torture-rtest-verilator - make torture-rtest-verilator
- stage: test - stage: test
name: run riscv benchmarks (serpent) name: run riscv benchmarks (Write-through Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-benchmarks-verilator defines=WT_DCACHE
# rv64ui-p-* tests # rv64ui-p-* tests
- stage: test - stage: test
name: run asm tests1 (serpent) name: run asm tests1 (Write-through Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-asm-tests1-verilator defines=WT_DCACHE
# rv64ui-v-* tests # rv64ui-v-* tests
- stage: test - stage: test
name: run asm tests2 (serpent) name: run asm tests2 (Write-through Cache)
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-asm-tests2-verilator defines=WT_DCACHE
# amo tests # amo tests
- stage: test - stage: test
name: run amo tests name: run amo tests
script: script:
- ci/build-riscv-tests.sh - ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-amo-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make -j${NUM_JOBS} run-amo-verilator defines=WT_DCACHE
- stage: test - stage: test
name: run torture (serpent) name: run torture (Write-through Cache)
script: script:
- ci/get-torture.sh - ci/get-torture.sh
- make clean - make clean
- make torture-gen defines=PITON_ARIANE+AXI64_CACHE_PORTS - make torture-gen defines=WT_DCACHE
- make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS - make torture-rtest-verilator defines=WT_DCACHE
# extra time during long builds # extra time during long builds
install: travis_wait install: travis_wait
...@@ -59,7 +59,7 @@ src/riscv-dbg/src/dm_pkg.sv ...@@ -59,7 +59,7 @@ src/riscv-dbg/src/dm_pkg.sv
include/riscv_pkg.sv include/riscv_pkg.sv
include/ariane_pkg.sv include/ariane_pkg.sv
include/ariane_axi_pkg.sv include/ariane_axi_pkg.sv
include/serpent_cache_pkg.sv include/wt_cache_pkg.sv
//include/std_cache_pkg.sv //include/std_cache_pkg.sv
include/axi_intf.sv include/axi_intf.sv
src/util/instruction_tracer_pkg.sv src/util/instruction_tracer_pkg.sv
...@@ -109,14 +109,14 @@ src/amo_buffer.sv ...@@ -109,14 +109,14 @@ src/amo_buffer.sv
src/store_unit.sv src/store_unit.sv
src/tlb.sv src/tlb.sv
src/commit_stage.sv src/commit_stage.sv
src/cache_subsystem/serpent_dcache_ctrl.sv src/cache_subsystem/wt_dcache_ctrl.sv
src/cache_subsystem/serpent_dcache_mem.sv src/cache_subsystem/wt_dcache_mem.sv
src/cache_subsystem/serpent_dcache_missunit.sv src/cache_subsystem/wt_dcache_missunit.sv
src/cache_subsystem/serpent_dcache_wbuffer.sv src/cache_subsystem/wt_dcache_wbuffer.sv
src/cache_subsystem/serpent_dcache.sv src/cache_subsystem/wt_dcache.sv
src/cache_subsystem/serpent_icache.sv src/cache_subsystem/wt_icache.sv
src/cache_subsystem/serpent_l15_adapter.sv src/cache_subsystem/wt_l15_adapter.sv
src/cache_subsystem/serpent_cache_subsystem.sv src/cache_subsystem/wt_cache_subsystem.sv
src/clint/clint.sv src/clint/clint.sv
src/clint/axi_lite_interface.sv src/clint/axi_lite_interface.sv
src/riscv-dbg/src/dm_csrs.sv src/riscv-dbg/src/dm_csrs.sv
......
...@@ -21,7 +21,7 @@ verilator ?= verilator ...@@ -21,7 +21,7 @@ verilator ?= verilator
# traget option # traget option
target-options ?= target-options ?=
# additional definess # additional definess
defines ?= defines ?= WT_DCACHE
# test name for torture runs (binary name) # test name for torture runs (binary name)
test-location ?= output/test test-location ?= output/test
# set to either nothing or -log # set to either nothing or -log
...@@ -55,7 +55,7 @@ ariane_pkg := include/riscv_pkg.sv \ ...@@ -55,7 +55,7 @@ ariane_pkg := include/riscv_pkg.sv \
src/riscv-dbg/src/dm_pkg.sv \ src/riscv-dbg/src/dm_pkg.sv \
include/ariane_pkg.sv \ include/ariane_pkg.sv \
include/std_cache_pkg.sv \ include/std_cache_pkg.sv \
include/serpent_cache_pkg.sv \ include/wt_cache_pkg.sv \
src/axi/src/axi_pkg.sv \ src/axi/src/axi_pkg.sv \
src/register_interface/src/reg_intf.sv \ src/register_interface/src/reg_intf.sv \
include/axi_intf.sv \ include/axi_intf.sv \
......
...@@ -220,23 +220,16 @@ You can read or write device memory by using: ...@@ -220,23 +220,16 @@ You can read or write device memory by using:
### Preliminary Support for OpenPiton Cache System ### Preliminary Support for OpenPiton Cache System
Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/serpent_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics. Ariane has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics.
The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the README in that repository to see how to use Ariane in the OpenPiton setting. The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use Ariane in the OpenPiton setting.
To activate the different cache system, compile your code with the macro `PITON_ARIANE`. To activate the different cache system, compile your code with the macro `WT_DCACHE` (set by default).
> For testing purposes, this L1 cache subsystem also supports AXI memory plugs in order to verify it within the Ariane CI environment. In order to use this feature, the macro `AXI64_CACHE_PORTS` has to be defined. Note however, that atomics are not supported in this configuration.
> Note that OpenPiton support is currently WIP, and although simple C programs run on one or several OpenPiton tiles, advanced features such as cache coherency are not fully verified yet.
Also, we are working on SMP Linux support on that platform - stay tuned!
## Planned Improvements ## Planned Improvements
Check-out the issue tab which also loosely tracks planned improvements. Check-out the issue tab which also loosely tracks planned improvements.
> Atomics are implemented for a single core environment. They will semantically fail in a multi-core setup (unless you are using the serpent flavor of Ariane in combination with the OpenPiton cache subsystem, see previous section).
## Going Beyond ## Going Beyond
......
...@@ -9,11 +9,11 @@ fi ...@@ -9,11 +9,11 @@ fi
if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then if [ ! -e "$VERILATOR_ROOT/bin/verilator" ]; then
echo "Installing Verilator" echo "Installing Verilator"
rm verilator*.t*gz rm -f verilator*.tgz
wget https://www.veripool.org/ftp/verilator-4.008.tgz wget https://www.veripool.org/ftp/verilator-4.008.tgz
tar xzf verilator*.t*gz tar xzf verilator*.tgz
rm verilator*.t*gz rm -f verilator*.tgz
cd verilator-* cd verilator*
mkdir -p $VERILATOR_ROOT mkdir -p $VERILATOR_ROOT
# copy scripts # copy scripts
autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS} autoconf && ./configure --prefix="$VERILATOR_ROOT" && make -j${NUM_JOBS}
......
...@@ -13,12 +13,13 @@ ...@@ -13,12 +13,13 @@
`define GENESYSII `define GENESYSII
`define PITON_FPGA_SYNTH
`define ARIANE_DATA_WIDTH 64 `define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker // Instantiate protocl checker
// `define PROTOCOL_CHECKER // `define PROTOCOL_CHECKER
// Use OpenPiton Caches // write-back cache
`define PITON_ARIANE // `define WB_DCACHE
`define AXI64_CACHE_PORTS
\ No newline at end of file // write-through cache
`define WT_DCACHE
...@@ -20,10 +20,8 @@ ...@@ -20,10 +20,8 @@
// configuration in case Ariane is // configuration in case Ariane is
// instantiated in OpenPiton // instantiated in OpenPiton
`ifdef PITON_ARIANE `ifdef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`include "l15.tmp.h" `include "l15.tmp.h"
`endif `endif
`endif
package ariane_pkg; package ariane_pkg;
...@@ -51,7 +49,7 @@ package ariane_pkg; ...@@ -51,7 +49,7 @@ package ariane_pkg;
// depth of store-buffers, this needs to be a power of two // depth of store-buffers, this needs to be a power of two
localparam int unsigned DEPTH_SPEC = 4; localparam int unsigned DEPTH_SPEC = 4;
`ifdef PITON_ARIANE `ifdef WT_DCACHE
// in this case we can use a small commit queue since we have a write buffer in the dcache // in this case we can use a small commit queue since we have a write buffer in the dcache
// we could in principle do without the commit queue in this case, but the timing degrades if we do that due // we could in principle do without the commit queue in this case, but the timing degrades if we do that due
// to longer paths into the commit stage // to longer paths into the commit stage
...@@ -63,15 +61,9 @@ package ariane_pkg; ...@@ -63,15 +61,9 @@ package ariane_pkg;
`ifdef PITON_ARIANE `ifdef PITON_ARIANE
`ifdef AXI64_CACHE_PORTS
// Floating-point extensions configuration
localparam bit RVF = 1'b0; // Is F extension enabled
localparam bit RVD = 1'b0; // Is D extension enabled
`else
// Floating-point extensions configuration // Floating-point extensions configuration
localparam bit RVF = 1'b0; // Is F extension enabled localparam bit RVF = 1'b0; // Is F extension enabled
localparam bit RVD = 1'b0; // Is D extension enabled localparam bit RVD = 1'b0; // Is D extension enabled
`endif
`else `else
// Floating-point extensions configuration // Floating-point extensions configuration
localparam bit RVF = 1'b0; // Is F extension enabled localparam bit RVF = 1'b0; // Is F extension enabled
...@@ -279,9 +271,7 @@ package ariane_pkg; ...@@ -279,9 +271,7 @@ package ariane_pkg;
// Cache config // Cache config
// --------------- // ---------------
// if serpent pulp is used standalone (outside of openpiton) // for usage in OpenPiton we have to propagate the openpiton L15 configuration from l15.h
// we just use the default config of ariane
// otherwise we have to propagate the openpiton L15 configuration from l15.h
`ifdef PITON_ARIANE `ifdef PITON_ARIANE
`ifndef CONFIG_L1I_CACHELINE_WIDTH `ifndef CONFIG_L1I_CACHELINE_WIDTH
......
...@@ -16,13 +16,11 @@ ...@@ -16,13 +16,11 @@
// configuration in case Ariane is // configuration in case Ariane is
// instantiated in OpenPiton // instantiated in OpenPiton
`ifdef PITON_ARIANE `ifdef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`include "l15.tmp.h" `include "l15.tmp.h"
`include "define.tmp.h" `include "define.tmp.h"
`endif `endif
`endif
package serpent_cache_pkg; package wt_cache_pkg;
// these parames need to coincide with the // these parames need to coincide with the
// L1.5 parameterization, do not change // L1.5 parameterization, do not change
...@@ -359,4 +357,4 @@ package serpent_cache_pkg; ...@@ -359,4 +357,4 @@ package serpent_cache_pkg;
return out; return out;
endfunction : paddrSizeAlign endfunction : paddrSizeAlign
endpackage : serpent_cache_pkg endpackage
...@@ -12,13 +12,6 @@ ...@@ -12,13 +12,6 @@
// Date: 19.03.2017 // Date: 19.03.2017
// Description: Ariane Top-level wrapper to break out SV structs to logic vectors. // Description: Ariane Top-level wrapper to break out SV structs to logic vectors.
// default to AXI64 cache ports if not using the
// serpent PULP extension
`ifndef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`define AXI64_CACHE_PORTS
`endif
`endif
module ariane_verilog_wrap #( module ariane_verilog_wrap #(
parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address
...@@ -39,31 +32,31 @@ module ariane_verilog_wrap #( ...@@ -39,31 +32,31 @@ module ariane_verilog_wrap #(
input time_irq_i, // timer interrupt in (async) input time_irq_i, // timer interrupt in (async)
input debug_req_i, // debug request (async) input debug_req_i, // debug request (async)
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
// L15 (memory side)
output [$size(wt_cache_pkg::l15_req_t)-1:0] l15_req_o,
input [$size(wt_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i
`else
// AXI (memory side) // AXI (memory side)
output [$size(ariane_axi::req_t)-1:0] axi_req_o, output [$size(ariane_axi::req_t)-1:0] axi_req_o,
input [$size(ariane_axi::resp_t)-1:0] axi_resp_i input [$size(ariane_axi::resp_t)-1:0] axi_resp_i
`else
// L15 (memory side)
output [$size(serpent_cache_pkg::l15_req_t)-1:0] l15_req_o,
input [$size(serpent_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i
`endif `endif
); );
// assign bitvector to packed struct and vice versa // assign bitvector to packed struct and vice versa
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
// L15 (memory side)
wt_cache_pkg::l15_req_t l15_req;
wt_cache_pkg::l15_rtrn_t l15_rtrn;
assign l15_req_o = l15_req;
assign l15_rtrn = l15_rtrn_i;
`else
ariane_axi::req_t axi_req; ariane_axi::req_t axi_req;
ariane_axi::resp_t axi_resp; ariane_axi::resp_t axi_resp;
assign axi_req_o = axi_req; assign axi_req_o = axi_req;
assign axi_resp = axi_resp_i; assign axi_resp = axi_resp_i;
`else
// L15 (memory side)
serpent_cache_pkg::l15_req_t l15_req;
serpent_cache_pkg::l15_rtrn_t l15_rtrn;
assign l15_req_o = l15_req;
assign l15_rtrn = l15_rtrn_i;
`endif `endif
...@@ -76,7 +69,7 @@ module ariane_verilog_wrap #( ...@@ -76,7 +69,7 @@ module ariane_verilog_wrap #(
// logic wake_up_d, wake_up_q; // logic wake_up_d, wake_up_q;
// logic rst_n; // logic rst_n;
// assign wake_up_d = wake_up_q || ((l15_rtrn.l15_returntype == serpent_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val); // assign wake_up_d = wake_up_q || ((l15_rtrn.l15_returntype == wt_cache_pkg::L15_INT_RET) && l15_rtrn.l15_val);
// always_ff @(posedge clk_i or negedge reset_l) begin : p_regs // always_ff @(posedge clk_i or negedge reset_l) begin : p_regs
// if(~reset_l) begin // if(~reset_l) begin
...@@ -171,12 +164,12 @@ module ariane_verilog_wrap #( ...@@ -171,12 +164,12 @@ module ariane_verilog_wrap #(
.ipi_i ( ipi ), .ipi_i ( ipi ),
.time_irq_i ( time_irq ), .time_irq_i ( time_irq ),
.debug_req_i ( debug_req ), .debug_req_i ( debug_req ),
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
.axi_req_o ( axi_req ),
.axi_resp_i ( axi_resp )
`else
.l15_req_o ( l15_req ), .l15_req_o ( l15_req ),
.l15_rtrn_i ( l15_rtrn ) .l15_rtrn_i ( l15_rtrn )
`else
.axi_req_o ( axi_req ),
.axi_resp_i ( axi_resp )
`endif `endif
); );
......
...@@ -13,27 +13,18 @@ ...@@ -13,27 +13,18 @@
// Description: Ariane Top-level module // Description: Ariane Top-level module
import ariane_pkg::*; import ariane_pkg::*;
//pragma translate_off // pragma translate_off
`ifndef VERILATOR `ifndef VERILATOR
import instruction_tracer_pkg::*; import instruction_tracer_pkg::*;
`endif `endif
//pragma translate_on // pragma translate_on
// default to AXI64 cache ports if not using the
// serpent PULP extension
`ifndef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`define AXI64_CACHE_PORTS
`endif
`endif
module ariane #( module ariane #(
parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address
parameter int unsigned AxiIdWidth = 4, parameter int unsigned AxiIdWidth = 4,
`ifdef PITON_ARIANE
parameter bit SwapEndianess = 0, // swap endianess in l15 adapter parameter bit SwapEndianess = 0, // swap endianess in l15 adapter
parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region
`endif
parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000 // begin of cached region parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000 // begin of cached region
) ( ) (
input logic clk_i, input logic clk_i,
...@@ -48,14 +39,14 @@ module ariane #( ...@@ -48,14 +39,14 @@ module ariane #(
// Timer facilities // Timer facilities
input logic time_irq_i, // timer interrupt in (async) input logic time_irq_i, // timer interrupt in (async)
input logic debug_req_i, // debug request (async) input logic debug_req_i, // debug request (async)
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
// L15 (memory side)
output wt_cache_pkg::l15_req_t l15_req_o,
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i
`else
// memory side, AXI Master // memory side, AXI Master
output ariane_axi::req_t axi_req_o, output ariane_axi::req_t axi_req_o,
input ariane_axi::resp_t axi_resp_i input ariane_axi::resp_t axi_resp_i
`else
// L15 (memory side)
output serpent_cache_pkg::l15_req_t l15_req_o,
input serpent_cache_pkg::l15_rtrn_t l15_rtrn_i
`endif `endif
); );
...@@ -335,7 +326,7 @@ module ariane #( ...@@ -335,7 +326,7 @@ module ariane #(
.trans_id_i ( {flu_trans_id_ex_id, load_trans_id_ex_id, store_trans_id_ex_id, fpu_trans_id_ex_id }), .trans_id_i ( {flu_trans_id_ex_id, load_trans_id_ex_id, store_trans_id_ex_id, fpu_trans_id_ex_id }),
.wbdata_i ( {flu_result_ex_id, load_result_ex_id, store_result_ex_id, fpu_result_ex_id }), .wbdata_i ( {flu_result_ex_id, load_result_ex_id, store_result_ex_id, fpu_result_ex_id }),
.ex_ex_i ( {flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id }), .ex_ex_i ( {flu_exception_ex_id, load_exception_ex_id, store_exception_ex_id, fpu_exception_ex_id }),
.wb_valid_i ( {flu_valid_ex_id, load_valid_ex_id, store_valid_ex_id, fpu_valid_ex_id }), .wt_valid_i ( {flu_valid_ex_id, load_valid_ex_id, store_valid_ex_id, fpu_valid_ex_id }),
.waddr_i ( waddr_commit_id ), .waddr_i ( waddr_commit_id ),
.wdata_i ( wdata_commit_id ), .wdata_i ( wdata_commit_id ),
...@@ -584,12 +575,10 @@ module ariane #( ...@@ -584,12 +575,10 @@ module ariane #(
// Cache Subsystem // Cache Subsystem
// ------------------- // -------------------
`ifdef PITON_ARIANE `ifdef WT_DCACHE
// this is a cache subsystem that is compatible with OpenPiton // this is a cache subsystem that is compatible with OpenPiton
serpent_cache_subsystem #( wt_cache_subsystem #(
`ifdef AXI64_CACHE_PORTS
.AxiIdWidth ( AxiIdWidth ), .AxiIdWidth ( AxiIdWidth ),
`endif
.CachedAddrBeg ( CachedAddrBeg ), .CachedAddrBeg ( CachedAddrBeg ),
.CachedAddrEnd ( CachedAddrEnd ), .CachedAddrEnd ( CachedAddrEnd ),
.SwapEndianess ( SwapEndianess ) .SwapEndianess ( SwapEndianess )
...@@ -618,13 +607,13 @@ module ariane #( ...@@ -618,13 +607,13 @@ module ariane #(
.dcache_req_ports_o ( dcache_req_ports_cache_ex ), .dcache_req_ports_o ( dcache_req_ports_cache_ex ),
// write buffer status // write buffer status
.wbuffer_empty_o ( dcache_commit_wbuffer_empty ), .wbuffer_empty_o ( dcache_commit_wbuffer_empty ),
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
.l15_req_o ( l15_req_o ),
.l15_rtrn_i ( l15_rtrn_i )
`else
// memory side // memory side
.axi_req_o ( axi_req_o ), .axi_req_o ( axi_req_o ),
.axi_resp_i ( axi_resp_i ) .axi_resp_i ( axi_resp_i )
`else
.l15_req_o ( l15_req_o ),
.l15_rtrn_i ( l15_rtrn_i )
`endif `endif
); );
`else `else
......
...@@ -14,11 +14,11 @@ ...@@ -14,11 +14,11 @@
// //
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_axi_adapter #( module wt_axi_adapter #(
parameter int unsigned ReqFifoDepth = 2, parameter int unsigned ReqFifoDepth = 2,
parameter int unsigned MetaFifoDepth = serpent_cache_pkg::DCACHE_MAX_TX, parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
parameter int unsigned AxiIdWidth = 4 parameter int unsigned AxiIdWidth = 4
) ( ) (
input logic clk_i, input logic clk_i,
...@@ -77,9 +77,9 @@ logic [2:0] amo_off_d, amo_off_q; ...@@ -77,9 +77,9 @@ logic [2:0] amo_off_d, amo_off_q;
// AMO generates r beat // AMO generates r beat
logic amo_gen_r_d, amo_gen_r_q; logic amo_gen_r_d, amo_gen_r_q;
logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q; logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q; logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
logic [serpent_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid; logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
logic dcache_rd_pop, dcache_wr_pop; logic dcache_rd_pop, dcache_wr_pop;
logic icache_rd_full, icache_rd_empty; logic icache_rd_full, icache_rd_empty;
logic dcache_rd_full, dcache_rd_empty; logic dcache_rd_full, dcache_rd_empty;
...@@ -161,16 +161,16 @@ always_comb begin : p_axi_req ...@@ -161,16 +161,16 @@ always_comb begin : p_axi_req
end else begin end else begin
unique case (dcache_data.rtype) unique case (dcache_data.rtype)
////////////////////////////////////// //////////////////////////////////////
serpent_cache_pkg::DCACHE_LOAD_REQ: begin wt_cache_pkg::DCACHE_LOAD_REQ: begin
axi_rd_req = 1'b1; axi_rd_req = 1'b1;
end end
////////////////////////////////////// //////////////////////////////////////
serpent_cache_pkg::DCACHE_STORE_REQ: begin wt_cache_pkg::DCACHE_STORE_REQ: begin
axi_wr_req = 1'b1; axi_wr_req = 1'b1;
axi_wr_be = serpent_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]); axi_wr_be = wt_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
end end
////////////////////////////////////// //////////////////////////////////////
serpent_cache_pkg::DCACHE_ATOMIC_REQ: begin wt_cache_pkg::DCACHE_ATOMIC_REQ: begin
// default // default
// push back an invalidation here. // push back an invalidation here.
// since we only keep one read tx in flight, and since // since we only keep one read tx in flight, and since
...@@ -178,7 +178,7 @@ always_comb begin : p_axi_req ...@@ -178,7 +178,7 @@ always_comb begin : p_axi_req
// an atomic, this is safe. // an atomic, this is safe.
invalidate = arb_gnt; invalidate = arb_gnt;
axi_wr_req = 1'b1; axi_wr_req = 1'b1;
axi_wr_be = serpent_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]); axi_wr_be = wt_cache_pkg::toByteEnable8(dcache_data.paddr[2:0], dcache_data.size[1:0]);
amo_gen_r_d = 1'b1; amo_gen_r_d = 1'b1;
// need to use a separate ID here, so concat an additional bit // need to use a separate ID here, so concat an additional bit
axi_wr_id_in[1] = 1'b1; axi_wr_id_in[1] = 1'b1;
...@@ -269,7 +269,7 @@ logic icache_rtrn_rd_en, dcache_rtrn_rd_en; ...@@ -269,7 +269,7 @@ logic icache_rtrn_rd_en, dcache_rtrn_rd_en;
logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q; logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q;
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_rd_icache_id ( ) i_rd_icache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
...@@ -286,7 +286,7 @@ fifo_v3 #( ...@@ -286,7 +286,7 @@ fifo_v3 #(
); );
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_rd_dcache_id ( ) i_rd_dcache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
...@@ -303,7 +303,7 @@ fifo_v3 #( ...@@ -303,7 +303,7 @@ fifo_v3 #(
); );
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( serpent_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_wr_dcache_id ( ) i_wr_dcache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
...@@ -353,14 +353,14 @@ fifo_v3 #( ...@@ -353,14 +353,14 @@ fifo_v3 #(
logic icache_first_d, icache_first_q, dcache_first_d, dcache_first_q; logic icache_first_d, icache_first_q, dcache_first_d, dcache_first_q;
logic [ICACHE_LINE_WIDTH/64-1:0][63:0] icache_rd_shift_d, icache_rd_shift_q; logic [ICACHE_LINE_WIDTH/64-1:0][63:0] icache_rd_shift_d, icache_rd_shift_q;
logic [DCACHE_LINE_WIDTH/64-1:0][63:0] dcache_rd_shift_d, dcache_rd_shift_q; logic [DCACHE_LINE_WIDTH/64-1:0][63:0] dcache_rd_shift_d, dcache_rd_shift_q;
serpent_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q; wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q;
serpent_cache_pkg::cache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q; wt_cache_pkg::cache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q;
logic dcache_sc_rtrn, axi_rd_last; logic dcache_sc_rtrn, axi_rd_last;
always_comb begin : p_axi_rtrn_shift always_comb begin : p_axi_rtrn_shift
// output directly from regs // output directly from regs
icache_rtrn_o = '0; icache_rtrn_o = '0;
icache_rtrn_o.rtype = serpent_cache_pkg::ICACHE_IFILL_ACK; icache_rtrn_o.rtype = wt_cache_pkg::ICACHE_IFILL_ACK;
icache_rtrn_o.tid = icache_rtrn_tid_q; icache_rtrn_o.tid = icache_rtrn_tid_q;
icache_rtrn_o.data = icache_rd_shift_q; icache_rtrn_o.data = icache_rd_shift_q;
icache_rtrn_vld_o = icache_rtrn_vld_q; icache_rtrn_vld_o = icache_rtrn_vld_q;
...@@ -422,7 +422,7 @@ always_comb begin : p_axi_rtrn_decode ...@@ -422,7 +422,7 @@ always_comb begin : p_axi_rtrn_decode
dcache_rd_pop = 1'b0; dcache_rd_pop = 1'b0;
dcache_wr_pop = 1'b0; dcache_wr_pop = 1'b0;
dcache_rtrn_inv_d = '0; dcache_rtrn_inv_d = '0;
dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_LOAD_ACK; dcache_rtrn_type_d = wt_cache_pkg::DCACHE_LOAD_ACK;
b_pop = 1'b0; b_pop = 1'b0;
dcache_sc_rtrn = 1'b0; dcache_sc_rtrn = 1'b0;
...@@ -435,7 +435,7 @@ always_comb begin : p_axi_rtrn_decode ...@@ -435,7 +435,7 @@ always_comb begin : p_axi_rtrn_decode
// write-through cache architecture, which is aligned with the openpiton // write-through cache architecture, which is aligned with the openpiton
// cache subsystem. // cache subsystem.
if (invalidate) begin if (invalidate) begin
dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_INV_REQ; dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ;
dcache_rtrn_vld_d = 1'b1; dcache_rtrn_vld_d = 1'b1;
dcache_rtrn_inv_d.all = 1'b1; dcache_rtrn_inv_d.all = 1'b1;
...@@ -450,7 +450,7 @@ always_comb begin : p_axi_rtrn_decode ...@@ -450,7 +450,7 @@ always_comb begin : p_axi_rtrn_decode
// if this was an atomic op // if this was an atomic op
if (axi_rd_id_out[1]) begin if (axi_rd_id_out[1]) begin
dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_ATOMIC_ACK; dcache_rtrn_type_d = wt_cache_pkg::DCACHE_ATOMIC_ACK;
// check if transaction was issued over write channel and pop that ID // check if transaction was issued over write channel and pop that ID
if (~dcache_wr_empty) begin if (~dcache_wr_empty) begin
...@@ -469,7 +469,7 @@ always_comb begin : p_axi_rtrn_decode ...@@ -469,7 +469,7 @@ always_comb begin : p_axi_rtrn_decode
// this was an atomic // this was an atomic
if (wr_id_out[1]) begin if (wr_id_out[1]) begin
dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_ATOMIC_ACK; dcache_rtrn_type_d = wt_cache_pkg::DCACHE_ATOMIC_ACK;
// silently discard b response if we already popped the fifo // silently discard b response if we already popped the fifo
// with a R beat (iff the amo transaction generated an R beat) // with a R beat (iff the amo transaction generated an R beat)
...@@ -480,7 +480,7 @@ always_comb begin : p_axi_rtrn_decode ...@@ -480,7 +480,7 @@ always_comb begin : p_axi_rtrn_decode
end end
end else begin end else begin
// regular response // regular response
dcache_rtrn_type_d = serpent_cache_pkg::DCACHE_STORE_ACK; dcache_rtrn_type_d = wt_cache_pkg::DCACHE_STORE_ACK;
dcache_rtrn_vld_d = 1'b1; dcache_rtrn_vld_d = 1'b1;
dcache_wr_pop = 1'b1; dcache_wr_pop = 1'b1;
end end
...@@ -510,7 +510,7 @@ always_ff @(posedge clk_i) begin : p_rd_buf ...@@ -510,7 +510,7 @@ always_ff @(posedge clk_i) begin : p_rd_buf
dcache_rtrn_vld_q <= '0; dcache_rtrn_vld_q <= '0;
icache_rtrn_tid_q <= '0; icache_rtrn_tid_q <= '0;
dcache_rtrn_tid_q <= '0; dcache_rtrn_tid_q <= '0;
dcache_rtrn_type_q <= serpent_cache_pkg::DCACHE_LOAD_ACK; dcache_rtrn_type_q <= wt_cache_pkg::DCACHE_LOAD_ACK;
dcache_rtrn_inv_q <= '0; dcache_rtrn_inv_q <= '0;
amo_off_q <= '0; amo_off_q <= '0;
amo_gen_r_q <= 1'b0; amo_gen_r_q <= 1'b0;
...@@ -582,4 +582,4 @@ axi_shim #( ...@@ -582,4 +582,4 @@ axi_shim #(
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_l15_adapter endmodule // wt_l15_adapter
\ No newline at end of file \ No newline at end of file
...@@ -14,17 +14,15 @@ ...@@ -14,17 +14,15 @@
// coherent memory system. // coherent memory system.
// //
// Define PITON_ARIANE if you want to use this cache. // Define PITON_ARIANE if you want to use this cache.
// Define AXI64_CACHE_PORTS if you want to use this cache // Define WT_DCACHE if you want to use this cache
// with a standard 64bit AXI interace instead of the openpiton // with a standard 64 bit AXI interface instead of the OpenPiton
// L1.5 interface. // L1.5 interface.
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_cache_subsystem #( module wt_cache_subsystem #(
`ifdef AXI64_CACHE_PORTS
parameter int unsigned AxiIdWidth = 10, parameter int unsigned AxiIdWidth = 10,
`endif
parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region
parameter bit SwapEndianess = 0 // swap endianess in l15 adapter parameter bit SwapEndianess = 0 // swap endianess in l15 adapter
...@@ -55,36 +53,34 @@ module serpent_cache_subsystem #( ...@@ -55,36 +53,34 @@ module serpent_cache_subsystem #(
output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
// writebuffer status // writebuffer status
output logic wbuffer_empty_o, output logic wbuffer_empty_o,
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
// memory side
output ariane_axi::req_t axi_req_o,
input ariane_axi::resp_t axi_resp_i
`else
// L15 (memory side) // L15 (memory side)
output l15_req_t l15_req_o, output l15_req_t l15_req_o,
input l15_rtrn_t l15_rtrn_i input l15_rtrn_t l15_rtrn_i
`else
// memory side
output ariane_axi::req_t axi_req_o,
input ariane_axi::resp_t axi_resp_i
`endif `endif
// TODO: interrupt interface // TODO: interrupt interface
); );
logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;
serpent_cache_pkg::icache_req_t icache_adapter; wt_cache_pkg::icache_req_t icache_adapter;
serpent_cache_pkg::icache_rtrn_t adapter_icache; wt_cache_pkg::icache_rtrn_t adapter_icache;
logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld; logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld;
serpent_cache_pkg::dcache_req_t dcache_adapter; wt_cache_pkg::dcache_req_t dcache_adapter;
serpent_cache_pkg::dcache_rtrn_t adapter_dcache; wt_cache_pkg::dcache_rtrn_t adapter_dcache;
serpent_icache #( wt_icache #(
`ifdef AXI64_CACHE_PORTS
.Axi64BitCompliant ( 1'b1 ), .Axi64BitCompliant ( 1'b1 ),
`endif
// use ID 0 for icache reads // use ID 0 for icache reads
.RdTxId ( 0 ), .RdTxId ( 0 ),
.CachedAddrBeg ( CachedAddrBeg ), .CachedAddrBeg ( CachedAddrBeg ),
.CachedAddrEnd ( CachedAddrEnd ) .CachedAddrEnd ( CachedAddrEnd )
) i_serpent_icache ( ) i_wt_icache (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.flush_i ( icache_flush_i ), .flush_i ( icache_flush_i ),
...@@ -106,16 +102,14 @@ serpent_icache #( ...@@ -106,16 +102,14 @@ serpent_icache #(
// Ports 0/1 for PTW and LD unit are read only. // Ports 0/1 for PTW and LD unit are read only.
// they have equal prio and are RR arbited // they have equal prio and are RR arbited
// Port 2 is write only and goes into the merging write buffer // Port 2 is write only and goes into the merging write buffer
serpent_dcache #( wt_dcache #(
`ifdef AXI64_CACHE_PORTS
.Axi64BitCompliant ( 1'b1 ), .Axi64BitCompliant ( 1'b1 ),
`endif
// use ID 1 for dcache reads and amos. note that the writebuffer // use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions. // uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
.RdAmoTxId ( 1 ), .RdAmoTxId ( 1 ),
.CachedAddrBeg ( CachedAddrBeg ), .CachedAddrBeg ( CachedAddrBeg ),
.CachedAddrEnd ( CachedAddrEnd ) .CachedAddrEnd ( CachedAddrEnd )
) i_serpent_dcache ( ) i_wt_dcache (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.enable_i ( dcache_enable_i ), .enable_i ( dcache_enable_i ),
...@@ -140,9 +134,9 @@ serpent_dcache #( ...@@ -140,9 +134,9 @@ serpent_dcache #(
// L15 cache interface (derived from OpenSPARC CCX). // L15 cache interface (derived from OpenSPARC CCX).
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
`ifdef AXI64_CACHE_PORTS `ifdef PITON_ARIANE
serpent_axi_adapter #( wt_l15_adapter #(
.AxiIdWidth ( AxiIdWidth ) .SwapEndianess ( SwapEndianess )
) i_adapter ( ) i_adapter (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -156,12 +150,12 @@ serpent_dcache #( ...@@ -156,12 +150,12 @@ serpent_dcache #(
.dcache_data_i ( dcache_adapter ), .dcache_data_i ( dcache_adapter ),
.dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ), .dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ),
.dcache_rtrn_o ( adapter_dcache ), .dcache_rtrn_o ( adapter_dcache ),
.axi_req_o ( axi_req_o ), .l15_req_o ( l15_req_o ),
.axi_resp_i ( axi_resp_i ) .l15_rtrn_i ( l15_rtrn_i )
); );
`else `else
serpent_l15_adapter #( wt_axi_adapter #(
.SwapEndianess ( SwapEndianess ) .AxiIdWidth ( AxiIdWidth )
) i_adapter ( ) i_adapter (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -175,8 +169,8 @@ serpent_dcache #( ...@@ -175,8 +169,8 @@ serpent_dcache #(
.dcache_data_i ( dcache_adapter ), .dcache_data_i ( dcache_adapter ),
.dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ), .dcache_rtrn_vld_o ( adapter_dcache_rtrn_vld ),
.dcache_rtrn_o ( adapter_dcache ), .dcache_rtrn_o ( adapter_dcache ),
.l15_req_o ( l15_req_o ), .axi_req_o ( axi_req_o ),
.l15_rtrn_i ( l15_rtrn_i ) .axi_resp_i ( axi_resp_i )
); );
`endif `endif
...@@ -207,4 +201,4 @@ serpent_dcache #( ...@@ -207,4 +201,4 @@ serpent_dcache #(
//pragma translate_on //pragma translate_on
endmodule // serpent_cache_subsystem endmodule // wt_cache_subsystem
...@@ -13,9 +13,9 @@ ...@@ -13,9 +13,9 @@
// Description: Instruction cache that is compatible with openpiton. // Description: Instruction cache that is compatible with openpiton.
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_dcache #( module wt_dcache #(
parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
// ID to be used for read and AMO transactions. // ID to be used for read and AMO transactions.
// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
...@@ -109,11 +109,11 @@ module serpent_dcache #( ...@@ -109,11 +109,11 @@ module serpent_dcache #(
// miss handling unit // miss handling unit
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
serpent_dcache_missunit #( wt_dcache_missunit #(
.Axi64BitCompliant ( Axi64BitCompliant ), .Axi64BitCompliant ( Axi64BitCompliant ),
.AmoTxId ( RdAmoTxId ), .AmoTxId ( RdAmoTxId ),
.NumPorts ( NumPorts ) .NumPorts ( NumPorts )
) i_serpent_dcache_missunit ( ) i_wt_dcache_missunit (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.enable_i ( enable_i ), .enable_i ( enable_i ),
...@@ -169,11 +169,11 @@ module serpent_dcache #( ...@@ -169,11 +169,11 @@ module serpent_dcache #(
// set these to high prio ports // set these to high prio ports
assign rd_prio[k] = 1'b1; assign rd_prio[k] = 1'b1;
serpent_dcache_ctrl #( wt_dcache_ctrl #(
.RdTxId ( RdAmoTxId ), .RdTxId ( RdAmoTxId ),
.CachedAddrBeg ( CachedAddrBeg ), .CachedAddrBeg ( CachedAddrBeg ),
.CachedAddrEnd ( CachedAddrEnd ) .CachedAddrEnd ( CachedAddrEnd )
) i_serpent_dcache_ctrl ( ) i_wt_dcache_ctrl (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.cache_en_i ( cache_en ), .cache_en_i ( cache_en ),
...@@ -215,10 +215,10 @@ module serpent_dcache #( ...@@ -215,10 +215,10 @@ module serpent_dcache #(
// set read port to low priority // set read port to low priority
assign rd_prio[2] = 1'b0; assign rd_prio[2] = 1'b0;
serpent_dcache_wbuffer #( wt_dcache_wbuffer #(
.CachedAddrBeg ( CachedAddrBeg ), .CachedAddrBeg ( CachedAddrBeg ),
.CachedAddrEnd ( CachedAddrEnd ) .CachedAddrEnd ( CachedAddrEnd )
) i_serpent_dcache_wbuffer ( ) i_wt_dcache_wbuffer (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.empty_o ( wbuffer_empty_o ), .empty_o ( wbuffer_empty_o ),
...@@ -270,10 +270,10 @@ module serpent_dcache #( ...@@ -270,10 +270,10 @@ module serpent_dcache #(
// memory arrays, arbitration and tag comparison // memory arrays, arbitration and tag comparison
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
serpent_dcache_mem #( wt_dcache_mem #(
.Axi64BitCompliant ( Axi64BitCompliant ), .Axi64BitCompliant ( Axi64BitCompliant ),
.NumPorts ( NumPorts ) .NumPorts ( NumPorts )
) i_serpent_dcache_mem ( ) i_wt_dcache_mem (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
// read ports // read ports
...@@ -329,4 +329,4 @@ module serpent_dcache #( ...@@ -329,4 +329,4 @@ module serpent_dcache #(
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_dcache endmodule // wt_dcache
...@@ -14,9 +14,9 @@ ...@@ -14,9 +14,9 @@
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_dcache_ctrl #( module wt_dcache_ctrl #(
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions
parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region
...@@ -271,4 +271,4 @@ end ...@@ -271,4 +271,4 @@ end
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_dcache_ctrl endmodule // wt_dcache_ctrl
\ No newline at end of file \ No newline at end of file
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
// //
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 13.09.2018 // Date: 13.09.2018
// Description: Memory arrays, arbiter and tag comparison for serpent dcache. // Description: Memory arrays, arbiter and tag comparison for wb dcache.
// //
// //
// Notes: 1) all ports can trigger a readout of all ways, and the way where the tag hits is selected // Notes: 1) all ports can trigger a readout of all ways, and the way where the tag hits is selected
...@@ -26,9 +26,9 @@ ...@@ -26,9 +26,9 @@
// low prio ports (rd_prio_i[port_nr] = '1b0) // low prio ports (rd_prio_i[port_nr] = '1b0)
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_dcache_mem #( module wt_dcache_mem #(
parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
parameter int unsigned NumPorts = 3 parameter int unsigned NumPorts = 3
) ( ) (
...@@ -235,10 +235,10 @@ module serpent_dcache_mem #( ...@@ -235,10 +235,10 @@ module serpent_dcache_mem #(
if (Axi64BitCompliant) begin if (Axi64BitCompliant) begin
assign wr_cl_off = (wr_cl_nc_i) ? '0 : wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3]; assign wr_cl_off = (wr_cl_nc_i) ? '0 : wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
end else begin end else begin
assign wr_cl_off = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3]; assign wr_cl_off = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
end end
assign rdata = (wr_cl_vld_i) ? wr_cl_data_i[wr_cl_off*64 +: 64] : assign rdata = (wr_cl_vld_i) ? wr_cl_data_i[wr_cl_off*64 +: 64] :
rdata_cl[rd_hit_idx]; rdata_cl[rd_hit_idx];
...@@ -262,7 +262,7 @@ module serpent_dcache_mem #( ...@@ -262,7 +262,7 @@ module serpent_dcache_mem #(
// Data RAM // Data RAM
sram #( sram #(
.DATA_WIDTH ( ariane_pkg::DCACHE_SET_ASSOC * 64 ), .DATA_WIDTH ( ariane_pkg::DCACHE_SET_ASSOC * 64 ),
.NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS ) .NUM_WORDS ( wt_cache_pkg::DCACHE_NUM_WORDS )
) i_data_sram ( ) i_data_sram (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -284,7 +284,7 @@ module serpent_dcache_mem #( ...@@ -284,7 +284,7 @@ module serpent_dcache_mem #(
sram #( sram #(
// tag + valid bit // tag + valid bit
.DATA_WIDTH ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ), .DATA_WIDTH ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ),
.NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS ) .NUM_WORDS ( wt_cache_pkg::DCACHE_NUM_WORDS )
) i_tag_sram ( ) i_tag_sram (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -335,8 +335,8 @@ module serpent_dcache_mem #( ...@@ -335,8 +335,8 @@ module serpent_dcache_mem #(
else $fatal(1,"[l1 dcache] wbuffer_hit_oh signal must be hot1"); else $fatal(1,"[l1 dcache] wbuffer_hit_oh signal must be hot1");
// this is only used for verification! // this is only used for verification!
logic vld_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0]; logic vld_mirror[wt_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0]; logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test; logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror
...@@ -376,4 +376,4 @@ module serpent_dcache_mem #( ...@@ -376,4 +376,4 @@ module serpent_dcache_mem #(
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_dcache_mem endmodule // wt_dcache_mem
...@@ -10,14 +10,14 @@ ...@@ -10,14 +10,14 @@
// //
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 13.09.2018 // Date: 13.09.2018
// Description: miss controller for serpent dcache. Note that the current assumption // Description: miss controller for wb dcache. Note that the current assumption
// is that the port with the highest index issues writes instead of reads. // is that the port with the highest index issues writes instead of reads.
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_dcache_missunit #( module wt_dcache_missunit #(
parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 3 // number of miss ports parameter int unsigned NumPorts = 3 // number of miss ports
...@@ -116,7 +116,7 @@ module serpent_dcache_missunit #( ...@@ -116,7 +116,7 @@ module serpent_dcache_missunit #(
assign cache_en_o = enable_q; assign cache_en_o = enable_q;
assign cnt_d = (flush_en) ? cnt_q + 1 : '0; assign cnt_d = (flush_en) ? cnt_q + 1 : '0;
assign flush_done = (cnt_q == serpent_cache_pkg::DCACHE_NUM_WORDS-1); assign flush_done = (cnt_q == wt_cache_pkg::DCACHE_NUM_WORDS-1);
assign miss_req_masked_d = ( lock_reqs ) ? miss_req_masked_q : assign miss_req_masked_d = ( lock_reqs ) ? miss_req_masked_q :
( mask_reads ) ? miss_we_i & miss_req_i : miss_req_i; ( mask_reads ) ? miss_we_i & miss_req_i : miss_req_i;
...@@ -216,7 +216,7 @@ module serpent_dcache_missunit #( ...@@ -216,7 +216,7 @@ module serpent_dcache_missunit #(
assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[DCACHE_OFFSET_WIDTH-1:3]*64 +: 64]; assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[DCACHE_OFFSET_WIDTH-1:3]*64 +: 64];
end end
endgenerate endgenerate
// always sign extend 32bit values // always sign extend 32bit values
assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}}, assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},
amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} : amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} :
...@@ -231,7 +231,7 @@ module serpent_dcache_missunit #( ...@@ -231,7 +231,7 @@ module serpent_dcache_missunit #(
assign mem_data_o.amo_op = (amo_sel) ? amo_req_i.amo_op : AMO_NONE; assign mem_data_o.amo_op = (amo_sel) ? amo_req_i.amo_op : AMO_NONE;
assign tmp_paddr = (amo_sel) ? amo_req_i.operand_a : miss_paddr_i[miss_port_idx]; assign tmp_paddr = (amo_sel) ? amo_req_i.operand_a : miss_paddr_i[miss_port_idx];
assign mem_data_o.paddr = serpent_cache_pkg::paddrSizeAlign(tmp_paddr, mem_data_o.size); assign mem_data_o.paddr = wt_cache_pkg::paddrSizeAlign(tmp_paddr, mem_data_o.size);
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
// responses from memory // responses from memory
...@@ -510,4 +510,4 @@ end ...@@ -510,4 +510,4 @@ end
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_dcache_missunit endmodule // wt_dcache_missunit
\ No newline at end of file \ No newline at end of file
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
// //
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 13.09.2018 // Date: 13.09.2018
// Description: coalescing write buffer for serpent dcache // Description: coalescing write buffer for wb dcache
// //
// A couple of notes: // A couple of notes:
// //
...@@ -49,9 +49,9 @@ ...@@ -49,9 +49,9 @@
// word has been evicted from the write buffer. // word has been evicted from the write buffer.
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_dcache_wbuffer #( module wt_dcache_wbuffer #(
parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000 // end of cached region
) ( ) (
...@@ -550,4 +550,4 @@ end ...@@ -550,4 +550,4 @@ end
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_dcache_wbuffer endmodule // wt_dcache_wbuffer
\ No newline at end of file \ No newline at end of file
...@@ -25,9 +25,9 @@ ...@@ -25,9 +25,9 @@
// //
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_icache #( module wt_icache #(
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions
parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter parameter bit Axi64BitCompliant = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region parameter logic [63:0] CachedAddrBeg = 64'h00_8000_0000, // begin of cached region
...@@ -530,8 +530,8 @@ module serpent_icache #( ...@@ -530,8 +530,8 @@ module serpent_icache #(
else $fatal(1,"[l1 icache] cl_hit signal must be hot1"); else $fatal(1,"[l1 icache] cl_hit signal must be hot1");
// this is only used for verification! // this is only used for verification!
logic vld_mirror[serpent_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0]; logic vld_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0]; logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test; logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror
...@@ -543,19 +543,19 @@ module serpent_icache #( ...@@ -543,19 +543,19 @@ module serpent_icache #(
if(vld_req[i] & vld_we) begin if(vld_req[i] & vld_we) begin
vld_mirror[vld_addr][i] <= vld_wdata[i]; vld_mirror[vld_addr][i] <= vld_wdata[i];
tag_mirror[vld_addr][i] <= cl_tag_q; tag_mirror[vld_addr][i] <= cl_tag_q;
end end
end end
end end
end end
generate generate
for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin
assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == cl_tag_q) & vld_mirror[vld_addr][i] & (|vld_wdata); assign tag_write_duplicate_test[i] = (tag_mirror[vld_addr][i] == cl_tag_q) & vld_mirror[vld_addr][i] & (|vld_wdata);
end end
endgenerate endgenerate
tag_write_duplicate: assert property ( tag_write_duplicate: assert property (
@(posedge clk_i) disable iff (~rst_ni) |vld_req |-> vld_we |-> ~(|tag_write_duplicate_test)) @(posedge clk_i) disable iff (~rst_ni) |vld_req |-> vld_we |-> ~(|tag_write_duplicate_test))
else $fatal(1,"[l1 icache] cannot allocate a CL that is already present in the cache"); else $fatal(1,"[l1 icache] cannot allocate a CL that is already present in the cache");
...@@ -567,4 +567,4 @@ module serpent_icache #( ...@@ -567,4 +567,4 @@ module serpent_icache #(
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_icache endmodule // wt_icache
...@@ -49,10 +49,10 @@ ...@@ -49,10 +49,10 @@
// //
import ariane_pkg::*; import ariane_pkg::*;
import serpent_cache_pkg::*; import wt_cache_pkg::*;
module serpent_l15_adapter #( module wt_l15_adapter #(
parameter bit SwapEndianess = 1 parameter bit SwapEndianess = 1
) ( ) (
input logic clk_i, input logic clk_i,
input logic rst_ni, input logic rst_ni,
...@@ -390,4 +390,4 @@ fifo_v2 #( ...@@ -390,4 +390,4 @@ fifo_v2 #(
`endif `endif
//pragma translate_on //pragma translate_on
endmodule // serpent_l15_adapter endmodule // wt_l15_adapter
\ No newline at end of file \ No newline at end of file
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