decoder: add logic output to say if there is a memory instruction

Signed-off-by: Alban Gruin <alban.gruin@irit.fr>

src/ariane.sv

@@ -89,6 +89,11 @@ module ariane import ariane_pkg::*; #(
   logic                     is_ctrl_fow_id_issue;
   logic                     issue_instr_issue_id;
 
+  // --------------
+  // ID -> verifier
+  // --------------
+  logic                     has_mem_access_id_verif;
+
   // --------------
   // ISSUE <-> EX
   // --------------
@@ -286,6 +291,7 @@ module ariane import ariane_pkg::*; #(
     .issue_entry_o              ( issue_entry_id_issue       ),
     .issue_entry_valid_o        ( issue_entry_valid_id_issue ),
     .is_ctrl_flow_o             ( is_ctrl_fow_id_issue       ),
+    .is_mem_instr_o             ( has_mem_access_id_verif    ),
     .issue_instr_ack_i          ( issue_instr_issue_id       ),
 
     .priv_lvl_i                 ( priv_lvl                   ),
@@ -626,6 +632,9 @@ module ariane import ariane_pkg::*; #(
     // IF
     .if_has_mem_access_i (has_mem_access_if_verif),
 
+    // ID
+    .id_has_mem_access_i (has_mem_access_id_verif),
+
     // CO
     .commit_instr_i (commit_instr_id_commit),
     .commit_ack_i (commit_ack)

src/id_stage.sv

@@ -37,7 +37,8 @@ module id_stage (
     input  logic                          debug_mode_i,        // we are in debug mode
     input  logic                          tvm_i,
     input  logic                          tw_i,
-    input  logic                          tsr_i
+    input  logic                          tsr_i,
+    output logic                          is_mem_instr_o
 );
     // ID/ISSUE register stage
     struct packed {
@@ -53,6 +54,8 @@ module id_stage (
     logic                [31:0] instruction;
     logic                is_compressed;
 
+    logic                is_mem_instr_n, is_mem_instr_q;
+
     // ---------------------------------------------------------
     // 1. Check if they are compressed and expand in case they are
     // ---------------------------------------------------------
@@ -94,25 +97,33 @@ module id_stage (
     assign issue_entry_valid_o = issue_q.valid;
     assign is_ctrl_flow_o = issue_q.is_ctrl_flow;
 
+    assign is_mem_instr_o = is_mem_instr_q;
+
     always_comb begin
         issue_n     = issue_q;
         fetch_entry_ready_o = 1'b0;
+        is_mem_instr_n = is_mem_instr_q;
 
         // Clear the valid flag if issue has acknowledged the instruction
-        if (issue_instr_ack_i)
+        if (issue_instr_ack_i) begin
             issue_n.valid = 1'b0;
+            is_mem_instr_n = 1'b0;
+        end
 
         // if we have a space in the register and the fetch is valid, go get it
         // or the issue stage is currently acknowledging an instruction, which means that we will have space
         // for a new instruction
         if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
-            fetch_entry_ready_o = 1'b1;
-            issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
+          fetch_entry_ready_o        = 1'b1;
+          issue_n                    = '{1'b1, decoded_instruction, is_control_flow_instr};
+          is_mem_instr_n = (decoded_instruction.fu == ariane_pkg::LOAD || decoded_instruction.fu == ariane_pkg::STORE);
         end
 
         // invalidate the pipeline register on a flush
-        if (flush_i)
+        if (flush_i) begin
             issue_n.valid = 1'b0;
+            is_mem_instr_n = 1'b0;
+        end
     end
     // -------------------------
     // Registers (ID <-> Issue)
@@ -120,8 +131,10 @@ module id_stage (
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if(~rst_ni) begin
             issue_q <= '0;
+            is_mem_instr_q <= '0;
         end else begin
             issue_q <= issue_n;
+            is_mem_instr_q <= is_mem_instr_n;
         end
     end
 endmodule

src/verifier.sv

@@ -9,6 +9,9 @@ module verifier #(
   // Frontend
   input logic                       if_has_mem_access_i,
 
+  // ID
+  input logic                       id_has_mem_access_i,
+
   // CO
   input                             ariane_pkg::scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
   input logic [NR_COMMIT_PORTS-1:0] commit_ack_i