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Commit edca53de authored by Alban Gruin's avatar Alban Gruin
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fpga: port Ariane to the Ultrascale ZCU104 


Signed-off-by: default avatarAlban Gruin <alban.gruin@irit.fr>
parent 7f7efd18
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Makefile
+ 7
− 34
View file @ edca53de
......@@ -62,9 +62,9 @@ app_path := $(root-dir)/sw/app
# board name for bitstream generation.
BOARD := zybo-z7-20
XILINX_PART := xc7z020clg400-1
XILINX_BOARD := digilentinc.com:zybo-z7-20:part0:1.0
BOARD := zcu104
XILINX_PART := xczu7ev-ffvc1156-2-e
XILINX_BOARD := xilinx.com:zcu104:part0:1.1
CLK_PERIOD_NS := 25
BATCH_MODE ?= 1
......@@ -194,9 +194,6 @@ src := $(addprefix $(root-dir), $(src))
uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
uart_src := $(addprefix $(root-dir), $(uart_src))
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches
tbs := tb/jtag_pkg.sv tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI)
......@@ -273,44 +270,20 @@ check-benchmarks:
benchmark:
cd sw/app && make $(APP).mem
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
# target rused to run synthesis and place and route in out of context mode
# make cva6_ooc CLK_PERIOD_NS=<period of the CVA6 architecture>
cva6_ooc: $(ariane_pkg) $(util) $(src) $(fpga_src)
@echo "Generate sources for synthesis"
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cva6_ooc:
cd fpga && make cva6_ooc BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
.PHONY: cva6_ooc cva6_fpga program_cva6_fpga
cva6_fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cva6_fpga:
@echo "[FPGA] Generate Bitstream"
cd fpga && make cva6_fpga BRAM=1 PS7_DDR=0 BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
cva6_fpga_ddr: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
@echo "[FPGA] Generate sources"
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
cva6_fpga_ddr:
@echo "[FPGA] Generate Bitstream"
cd fpga && make cva6_fpga PS7_DDR=1 BRAM=0 XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
cd fpga && make cva6_fpga PS7_DDR=1 BRAM=0 BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
program_cva6_fpga:
......
fpga/Makefile
+ 14
− 19
View file @ edca53de
......@@ -32,13 +32,15 @@ VIVADO ?= vivado
work-dir := work-fpga
bit := $(work-dir)/cva6_fpga.bit
mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
root-dir := $(dir $(mkfile_path))
project_dir := $(abspath $(root-dir)/..)
ip-dir := xilinx
ips := xlnx_blk_mem_gen.xci \
xlnx_processing_system7.xci \
xlnx_axi_clock_converter.xci \
xlnx_axi_dwidth_converter_dm_master.xci \
xlnx_axi_dwidth_converter_dm_slave.xci \
xlnx_clk_gen.xci
ips := $(ip-dir)/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci \
$(ip-dir)/xlnx_clk_gen/ip/xlnx_clk_gen.xci \
$(ip-dir)/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci \
$(ip-dir)/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
all: $(cva6_ooc)
......@@ -51,28 +53,20 @@ endif
cva6_fpga: $(ips)
ifeq ($(BATCH_MODE), 1)
mkdir -p $(work-dir)
$(VIVADO) -mode batch -source scripts/run_cva6_fpga.tcl
@ EXT_IPS="$(ips)" ARIANE_SRC=$(project_dir) FPGA_SRC=$(root-dir)/src $(VIVADO) -mode batch -source scripts/run_cva6_fpga.tcl
else
$(VIVADO) -source scripts/run_cva6_fpga.tcl
$(VIVADO) -source scripts/run_cva6_fpga.tcl
endif
program_cva6_fpga:
xsct scripts/program_cva6_fpga.tcl
get_hs2_sn:
$(VIVADO) -mode batch -source scripts/get_hs2_sn.tcl
$(ips): %.xci :
mkdir -p $(work-dir)
%.xci:
@echo Generating $(@F)
@cd $(ip-dir)/$(basename $(@F)) && make clean && make
@cp $(ip-dir)/$(basename $(@F))/ip/$(@F) $@
clean:
rm -rf *.log \
......@@ -88,6 +82,7 @@ clean:
cva6_ooc.runs \
cva6_ooc.hbs \
cva6_fpga.cache \
cva6_fpga.srcs \
cva6_fpga.hw \
cva6_fpga.ip_user_files \
cva6_fpga.sim \
......@@ -98,8 +93,8 @@ clean:
reports_cva6_ooc_impl \
reports_cva6_fpga_synth \
reports_cva6_fpga_impl \
$(work-dir)
$(work-dir) \
$(ips)
.PHONY:
clean
fpga/constraints/cva6_fpga.xdc
+ 1
− 3
View file @ edca53de
......@@ -2,7 +2,7 @@
create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports tck]
set_input_jitter tck 1.000
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets tck]
# minimize routing delay
set_input_delay -clock tck -clock_fall 5.000 [get_ports tdi]
......@@ -18,5 +18,3 @@ set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_ds
# set multicycle path on reset, on the FPGA we do not care about the reset anyway
set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
fpga/constraints/zcu104.xdc 0 → 100644
+ 38
− 0
View file @ edca53de
# set_property PACKAGE_PIN F23 [get_ports clk_sys_p]
# set_property IOSTANDARD LVDS [get_ports clk_sys_p]
# set_property PACKAGE_PIN E23 [get_ports clk_sys_n]
# set_property IOSTANDARD LVDS [get_ports clk_sys_n]
# set_property PACKAGE_PIN AH18 [get_ports clk_sys_p]
# set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk_sys_p]
# set_property PACKAGE_PIN AH17 [get_ports clk_sys_n]
# set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk_sys_n]
set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVDS} [get_ports clk_sys_p]
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVDS} [get_ports clk_sys_n]
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports reset]
## To use FTDI FT2232 JTAG
set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports trst_n]
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS33} [get_ports tck]
set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports tdi]
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports tdo]
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS33} [get_ports tms]
## UART
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports tx]
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports rx]
## JTAG
# minimize routing delay
set_max_delay -to [get_ports tdo] 20.000
set_max_delay -from [get_ports tms] 20.000
set_max_delay -from [get_ports tdi] 20.000
set_max_delay -from [get_ports trst_n] 20.000
# reset signal
set_false_path -from [get_ports trst_n]
fpga/scripts/program_cva6_fpga.tcl
+ 1
− 5
View file @ edca53de
......@@ -5,12 +5,8 @@ targets -set -nocase -filter {name =~"APU*"}
rst -system
after 3000
#targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351AD67C0A" && level==0 && jtag_device_ctx=="jsn-Zybo Z7-210351AD67C0A-23727093-0"}
fpga -file cva6_fpga.runs/impl_1/cva6_zybo_z7_20.bit
fpga -file cva6_fpga.runs/impl_1/cva6_ultrascale.bit
#targets -set -nocase -filter {name =~"APU*"}
#loadhw -hw /home/sjacq/Work_dir/USE_CASE/2020/contest_softcore_cva6/migration2github/test/workspace/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa -mem-ranges [list {0x40000000 0xbfffffff}] -regs
#configparams force-mem-access 1
targets -set -nocase -filter {name =~"APU*"}
source scripts/ps7_init.tcl
ps7_init
ps7_post_config
fpga/scripts/run_cva6_fpga.tcl
+ 30
− 46
View file @ edca53de
......@@ -27,63 +27,53 @@
# Date Version Author Description
# 2020-11-06 0.1 S.Jacq Created
# =========================================================================== #
set project cva6_fpga
set src_dir $::env(ARIANE_SRC)/src
set include_dir $::env(ARIANE_SRC)/include
set fpga_src_dir $::env(FPGA_SRC)
set ext_ips $::env(EXT_IPS)
set top_module cva6_ultrascale
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
# Adding all files recursively from src, include and fpga
add_files -scan_for_includes $src_dir $include_dir $fpga_src_dir
read_ip $ext_ips
# Removing duplicate files
remove_files [get_files -regexp [list ".*/fpu/.*/popcount.sv" ".*/fpu/.*/registers.svh" ".*/pmp/.*/riscv.sv"]]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-4480]} -limit 1000
add_files -fileset constrs_1 -norecurse constraints/zybo_z7_20.xdc
read_ip xilinx/xlnx_processing_system7/ip/xlnx_processing_system7.xci
read_ip xilinx/xlnx_blk_mem_gen/ip/xlnx_blk_mem_gen.xci
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
read_ip xilinx/xlnx_axi_dwidth_converter_dm_slave/ip/xlnx_axi_dwidth_converter_dm_slave.xci
read_ip xilinx/xlnx_axi_dwidth_converter_dm_master/ip/xlnx_axi_dwidth_converter_dm_master.xci
read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci
# Defining registers.svh as a global header
set global_headers [list ".*/registers.svh" ".*/zybo-z7-20.svh"]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects [get_files -regexp $global_headers]
set_property include_dirs { "src/axi_sd_bridge/include" "../src/common_cells/include" } [current_fileset]
source scripts/add_sources.tcl
# Setting top module
set_property top $top_module [get_filesets sources_1]
set_property top cva6_zybo_z7_20 [current_fileset]
read_verilog -sv {../src/common_cells/include/common_cells/registers.svh}
set registers "../src/common_cells/include/common_cells/registers.svh"
read_verilog -sv {src/zybo-z7-20.svh src/zybo-z7-20-ddr.svh ../src/common_cells/include/common_cells/registers.svh}
#set file "src/zybo-z7-20.svh"
if { $::env(PS7_DDR) == 1 } {
set file "src/zybo-z7-20-ddr.svh"
} elseif {$::env(BRAM) == 1} {
set file "src/zybo-z7-20.svh"
} else {
puts "None of the values is matching"
}
# Disable unused files
reorder_files -auto -disable_unused -fileset [get_filesets sources_1]
set registers "../src/common_cells/include/common_cells/registers.svh"
# Remove disabled files
# remove_files [get_files -filter {!IS_ENABLED}]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]]
set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
set_msg_config -id {[Synth 8-4480]} -limit 1000
update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse constraints/cva6_fpga.xdc
add_files -fileset constrs_1 -norecurse constraints/zcu104.xdc
add_files -fileset constrs_1 -norecurse constraints/$project.xdc
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
update_compile_order -fileset [get_filesets sources_1]
# synth_design -verilog_define PS7_DDR=$::env(PS7_DDR) -verilog_define BRAM=$::env(BRAM) -rtl -name rtl_1
if { $::env(PS7_DDR) == 1 } {
synth_design -verilog_define PS7_DDR=PS7_DDR -rtl -name rtl_1
} elseif {$::env(BRAM) == 1} {
synth_design -verilog_define BRAM=BRAM -rtl -name rtl_1
} else {
puts "None of the values is matching"
}
set_property generate_synth_checkpoint 0 [get_files $ext_ips]
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
......@@ -94,7 +84,6 @@ open_run synth_1
exec mkdir -p reports_cva6_fpga_synth/
exec rm -rf reports_cva6_fpga_synth/*
check_timing -verbose -file reports_cva6_fpga_synth/$project.check_timing.rpt
report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_synth/$project.timing_WORST_100.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_fpga_synth/$project.timing.rpt
......@@ -106,11 +95,6 @@ report_clock_interaction -file re
set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
##create_clock -period $::env(CLK_PERIOD_NS) -name clk_i [get_ports clk_i]
#set_property HD.CLK_SRC BUFGCTRL_X1Y2 [get_ports clk_i]
launch_runs impl_1
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream
......
fpga/src/ariane_soc_pkg.sv 0 → 100644
+ 95
− 0
View file @ edca53de
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Florian Zaruba, ETH Zurich
// Description: Contains SoC information as constants
package ariane_soc;
// M-Mode Hart, S-Mode Hart
localparam int unsigned NumTargets = 2;
// Uart, SPI, Ethernet, reserved
localparam int unsigned NumSources = 30;
localparam int unsigned MaxPriority = 7;
localparam NrSlaves = 2; // actually masters, but slaves on the crossbar
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam IdWidthSlave = IdWidth + $clog2(NrSlaves);
typedef enum int unsigned {
DRAM = 0,
GPIO = 1,
Ethernet = 2,
SPI = 3,
Timer = 4,
UART = 5,
PLIC = 6,
CLINT = 7,
ROM = 8,
Debug = 9
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h10000;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h1000;
localparam logic[63:0] TimerLength = 64'h1000;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] GPIOLength = 64'h1000;
localparam logic[63:0] DRAMLength = 64'h40000000; // 1GByte of DDR (split between two chips on Genesys2)
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;
typedef enum logic [63:0] {
DebugBase = 64'h0000_0000,
ROMBase = 64'h0001_0000,
CLINTBase = 64'h0200_0000,
PLICBase = 64'h0C00_0000,
UARTBase = 64'h1000_0000,
TimerBase = 64'h1800_0000,
SPIBase = 64'h2000_0000,
EthernetBase = 64'h3000_0000,
GPIOBase = 64'h4000_0000,
DRAMBase = 64'h8000_0000
} soc_bus_start_t;
localparam NrRegion = 1;
localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
// idempotent region
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {64'b0},
NonIdempotentLength: {DRAMBase},
NrExecuteRegionRules: 3,
ExecuteRegionAddrBase: {DRAMBase, ROMBase, DebugBase},
ExecuteRegionLength: {DRAMLength, ROMLength, DebugLength},
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {DRAMBase},
CachedRegionLength: {DRAMLength},
// cache config
Axi64BitCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: DebugBase,
NrPMPEntries: 8
};
endpackage
fpga/src/cva6_ultrascale.sv 0 → 100644
+ 704
− 0
View file @ edca53de
This diff is collapsed.
fpga/src/zybo-z7-20.svh
+ 1
− 1
View file @ edca53de
......@@ -11,7 +11,7 @@
`define WT_DCACHE
// debug probe
`define LAUTERBACH_DEBUG_PROBE
// `define LAUTERBACH_DEBUG_PROBE
// to use BRAM in FPGA fabric
`define BRAM
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
+ 3
− 1
View file @ edca53de
......@@ -10,10 +10,12 @@ create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PRIM_IN_FREQ {125.000} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
CONFIG.CLKOUT1_USED {true} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \
......
fpga/xilinx/xlnx_processing_system7/tcl/run.tcl
+ 10
− 97
View file @ edca53de
......@@ -6,104 +6,17 @@ set ipName xlnx_processing_system7
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name processing_system7 -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_CLK0_FREQ {10000000} \
CONFIG.PCW_CLK1_FREQ {10000000} \
CONFIG.PCW_CLK2_FREQ {10000000} \
CONFIG.PCW_CLK3_FREQ {10000000} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_EN_CLK0_PORT {0} \
CONFIG.PCW_EN_RST0_PORT {0} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK0_BUF {FALSE} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_BL {8} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.221} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.222} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.217} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.244} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.05} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.044} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.035} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.100} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_USE_M_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
] [get_ips $ipName]
create_ip -name zynq_ultra_ps_e -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list \
CONFIG.PSU__USE__M_AXI_GP0 {0} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__USE__S_AXI_GP2 {1} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USE__FABRIC__RST {0} \
CONFIG.PSU__FPGA_PL0_ENABLE {0} \
CONFIG.PSU__USE__IRQ0 {0} \
] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
......
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