Replace dtor by a coccinelle patch, use -Os instead of -O3, lighter destructor

Signed-off-by: Alban Gruin <alban.gruin@univ-tlse3.fr>

.gitignore

 bench/build/
+bench/sic.patch
 

bench/Makefile

@@ -57,29 +57,41 @@ kernels = \
 	isqrt \
 	jfdctint \
 	lms \
+	ludcmp \
 	matrix1 \
 	md5 \
 	minver \
+	pm \
 	prime \
+	quicksort \
 	rad2deg \
 	recursion \
+	sha \
 	st
 
 sequentials = \
 	adpcm_dec \
-    adpcm_enc \
-    cjpeg_transupp \
-    cjpeg_wrbmp \
-    dijkstra \
-    fmref \
-    g723_enc \
-    gsm_dec \
-    h264_dec \
-    huff_dec \
-    huff_enc \
-    ndes \
-    petrinet \
-    statemate
+	adpcm_enc \
+	ammunition \
+	anagram \
+	audiobeam \
+	cjpeg_transupp \
+	cjpeg_wrbmp \
+	dijkstra \
+	epic \
+	fmref \
+	g723_enc \
+	gsm_dec \
+	gsm_enc \
+	h264_dec \
+	huff_dec \
+	huff_enc \
+	ndes \
+	petrinet \
+	rijndael_dec \
+	rijndael_enc \
+	statemate \
+	susan
 
 bmarks = $(addprefix kernel/,$(kernels)) $(addprefix sequential/,$(sequentials))
 
@@ -96,22 +108,24 @@ RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
 SRC_BSP_C = $(wildcard $(bsp_dir)/hal/*.c) $(wildcard $(bsp_dir)/drivers/uart/*.c)
 SRC_BSP_S = $(wildcard $(bsp_dir)/hal/*.S)
 
+COCCI_SRC_FILES = $(shell find kernel/ sequential/ -type f -name "*.c")
+
 OBJ_BSP_C = $(addprefix build/,$(SRC_BSP_C:.c=.o))
 OBJ_BSP_S = $(addprefix build/,$(SRC_BSP_S:.S=.o))
 OBJ_BSP = $(OBJ_BSP_S) $(OBJ_BSP_C)
 
 BSP_INCS = -Ibsp/config -Ibsp/drivers/uart -Ibsp/hal
-INCS = $(BSP_INCS)
+INCS = $(BSP_INCS) -Isic
 
 FLAGS_STR := "$(RISCV_CFLAGS)  $(RISCV_LDFLAGS) "
 
-CFLAGS ?= -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic
+CFLAGS ?= -DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -Os -mcmodel=medany -static -Wall -pedantic
 
 RISCV_CFLAGS := -DPERFORMANCE_RUN=1 \
 		-DITERATIONS=3 \
 		-DFLAGS_STR=\"$(FLAGS_STR)\" \
 		-Wno-unknown-pragmas \
-		-DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -O3 -mcmodel=medany -static -Wall -pedantic
+		-DPREALLOCATE=1 -fvisibility=hidden -DSTDIO_THRU_UART -Os -mcmodel=medany -static -Wall -pedantic
 
 RISCV_LDFLAGS = -Lbuild/ -lcva6 -static -nostartfiles -T bsp/config/link.ld
 
@@ -130,7 +144,7 @@ $(1): build/artifacts/$(1).D
 $(1): build/artifacts/$(1).hex
 $(1): build/artifacts/$(1).bin
 $(1): build/mem/$(1).mem
-build/artifacts/$(1).riscv: build/libcva6.a build/dtor.o $$($(1)_OBJ_FILES)
+build/artifacts/$(1).riscv: build/libcva6.a $$($(1)_OBJ_FILES)
 	$$(DIR_GUARD)
 	@echo " LD	$$@"
 	@$$(RISCV_GCC) $$(RISCV_CFLAGS) -o $$@ $$^ $$(RISCV_LDFLAGS)
@@ -153,10 +167,10 @@ build/artifacts/%.bin: build/artifacts/%.riscv
 	@echo " OBJCOPY	$< -> $@"
 	@$(RISCV_OBJCOPY) -O binary $< $@
 
-build/libcva6.a: $(OBJ_BSP)
+build/libcva6.a: $(OBJ_BSP) build/sic/siccsrs.o
 	$(DIR_GUARD)
 	@echo " AR	$< -> $@"
-	@$(RISCV_AR) rcs build/libcva6.a $(OBJ_BSP)
+	@$(RISCV_AR) rcs build/libcva6.a $^
 
 build/%.o: %.c
 	$(DIR_GUARD)
@@ -173,8 +187,12 @@ build/mem/%.mem: build/artifacts/%.bin
 	@echo " BIN2MEM	$< -> $@"
 	@$(utils_dir)/bin2mem.py $< $@
 
+sic.patch: sic.cocci
+	@echo " SPATCH $<"
+	@spatch --sp-file $< $(COCCI_SRC_FILES) --patch . >$@
+
 clean:
 	@echo " RM	build/"
-	@rm -rf build/
+	@rm -rf build/ sic.patch
 
 .PHONY: all clean

bench/sic.cocci

+@@
+@@
+
++ #include <siccsrs.h>
+
+int main(void)
+{
+...
+
++ siccsrs();
+
+  return ...;
+}

bench/dtor.c → bench/sic/siccsrs.c

@@ -2,10 +2,20 @@
 #include <stdio.h>
 #include <stdlib.h>
 
+#include "siccsrs.h"
+
 #define READCSR(_t, counter)                    \
-  asm volatile("csrr %0, " # counter : "=r" (_t))
+  asm volatile ("csrr %0, " # counter : "=r" (_t))
+
+static inline void print_uint(const char *msg, uint32_t val) {
+    char buffer[sizeof(uint32_t) * 8 + 1] = {0};
+
+    utoa(val, buffer, 10);
+    fputs(msg, stdout);
+    fputs(buffer, stdout);
+}
 
-static void __attribute__((destructor)) dtor(void) {
+void siccsrs(void) {
     uint32_t brpending, mempending, lsu, imiss;
 
     READCSR(brpending, 0xB11);
@@ -13,8 +23,9 @@ static void __attribute__((destructor)) dtor(void) {
     READCSR(lsu, 0xB13);
     READCSR(imiss, 0xB14);
 
-    printf("==== dtor ====\n"
-           "brpending: %ld; mempending: %ld; lsu: %ld; imiss: %ld\n"
-           "==== end of dtor ====\n",
-           brpending, mempending, lsu, imiss);
+    print_uint("brpending: ", brpending);
+    print_uint("; mempending: ", mempending);
+    print_uint("; lsu: ", lsu);
+    print_uint("; imiss: ", imiss);
+    puts("");
 }

bench/sic/siccsrs.h

+#ifndef __SICCSRS_H_
+#define __SICCSRS_H_
+
+void siccsrs(void);
+
+#endif  /* __SICCSRS_H_ */