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Commit 95e099ca authored by Michael Schaffner's avatar Michael Schaffner Committed by Florian Zaruba
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common_cells: Bump and remove deprecated modules

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Flist.ariane
+ 0
− 5
View file @ 95e099ca
...@@ -17,19 +17,14 @@ ...@@ -17,19 +17,14 @@
// Description: File list for OpenPiton flow // Description: File list for OpenPiton flow
+incdir+src/common_cells/include/common_cells/ +incdir+src/common_cells/include/common_cells/
+incdir+src/util/ +incdir+src/util/
src/common_cells/src/deprecated/fifo_v1.sv
src/common_cells/src/deprecated/fifo_v2.sv
src/common_cells/src/fifo_v3.sv src/common_cells/src/fifo_v3.sv
src/common_cells/src/lfsr_8bit.sv src/common_cells/src/lfsr_8bit.sv
src/common_cells/src/lzc.sv src/common_cells/src/lzc.sv
src/common_cells/src/rr_arb_tree.sv src/common_cells/src/rr_arb_tree.sv
src/common_cells/src/deprecated/rrarbiter.sv
src/common_cells/src/rstgen_bypass.sv src/common_cells/src/rstgen_bypass.sv
src/common_cells/src/sync.sv src/common_cells/src/sync.sv
src/common_cells/src/sync_wedge.sv src/common_cells/src/sync_wedge.sv
src/common_cells/src/cdc_2phase.sv src/common_cells/src/cdc_2phase.sv
src/common_cells/src/deprecated/stream_arbiter.sv
src/common_cells/src/deprecated/stream_arbiter_flushable.sv
src/common_cells/src/shift_reg.sv src/common_cells/src/shift_reg.sv
src/register_interface/src/apb_to_reg.sv src/register_interface/src/apb_to_reg.sv
src/register_interface/src/reg_intf_pkg.sv src/register_interface/src/reg_intf_pkg.sv
......
Makefile
+ 4
− 4
View file @ 95e099ca
...@@ -137,8 +137,6 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ ...@@ -137,8 +137,6 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
src/common_cells/src/rstgen.sv \ src/common_cells/src/rstgen.sv \
src/common_cells/src/stream_mux.sv \ src/common_cells/src/stream_mux.sv \
src/common_cells/src/stream_demux.sv \ src/common_cells/src/stream_demux.sv \
src/common_cells/src/deprecated/stream_arbiter.sv \
src/common_cells/src/deprecated/stream_arbiter_flushable.sv \
src/util/axi_master_connect.sv \ src/util/axi_master_connect.sv \
src/util/axi_slave_connect.sv \ src/util/axi_slave_connect.sv \
src/util/axi_master_connect_rev.sv \ src/util/axi_master_connect_rev.sv \
...@@ -153,9 +151,11 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \ ...@@ -153,9 +151,11 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
src/common_cells/src/spill_register.sv \ src/common_cells/src/spill_register.sv \
src/common_cells/src/sync_wedge.sv \ src/common_cells/src/sync_wedge.sv \
src/common_cells/src/edge_detect.sv \ src/common_cells/src/edge_detect.sv \
src/common_cells/src/fifo_v3.sv \ src/common_cells/src/deprecated/stream_arbiter.sv \
src/common_cells/src/deprecated/fifo_v2.sv \ src/common_cells/src/deprecated/stream_arbiter_flushable.sv \
src/common_cells/src/deprecated/fifo_v1.sv \ src/common_cells/src/deprecated/fifo_v1.sv \
src/common_cells/src/deprecated/fifo_v2.sv \
src/common_cells/src/fifo_v3.sv \
src/common_cells/src/lzc.sv \ src/common_cells/src/lzc.sv \
src/common_cells/src/rr_arb_tree.sv \ src/common_cells/src/rr_arb_tree.sv \
src/common_cells/src/deprecated/rrarbiter.sv \ src/common_cells/src/deprecated/rrarbiter.sv \
......
src/amo_buffer.sv
+ 2
− 5
View file @ 95e099ca
...@@ -60,10 +60,8 @@ module amo_buffer ( ...@@ -60,10 +60,8 @@ module amo_buffer (
// e.g.: it is not speculative anymore // e.g.: it is not speculative anymore
assign flush_amo_buffer = flush_i & !amo_valid_commit_i; assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
fifo_v2 #( fifo_v3 #(
.DEPTH ( 1 ), .DEPTH ( 1 ),
.ALM_EMPTY_TH ( 0 ),
.ALM_FULL_TH ( 0 ),
.dtype ( amo_op_t ) .dtype ( amo_op_t )
) i_amo_fifo ( ) i_amo_fifo (
.clk_i ( clk_i ), .clk_i ( clk_i ),
...@@ -72,8 +70,7 @@ module amo_buffer ( ...@@ -72,8 +70,7 @@ module amo_buffer (
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( amo_valid ), .full_o ( amo_valid ),
.empty_o ( ready_o ), .empty_o ( ready_o ),
.alm_full_o ( ), // left open .usage_o ( ), // left open
.alm_empty_o ( ), // left open
.data_i ( amo_data_in ), .data_i ( amo_data_in ),
.push_i ( valid_i ), .push_i ( valid_i ),
.data_o ( amo_data_out ), .data_o ( amo_data_out ),
......
src/cache_subsystem/wt_axi_adapter.sv
+ 24
− 21
View file @ 95e099ca
...@@ -98,18 +98,23 @@ module wt_axi_adapter #( ...@@ -98,18 +98,23 @@ module wt_axi_adapter #(
assign arb_gnt = axi_rd_gnt | axi_wr_gnt; assign arb_gnt = axi_rd_gnt | axi_wr_gnt;
rrarbiter #( rr_arb_tree #(
.NUM_REQ(2), .NumIn (2),
.LOCK_IN(1) .DataWidth (1),
) i_rrarbiter ( .AxiVldRdy (1'b1),
.clk_i ( clk_i ), .LockIn (1'b1)
.rst_ni ( rst_ni ), ) i_rr_arb_tree (
.flush_i( '0 ), .clk_i (clk_i ),
.en_i ( arb_gnt ), .rst_ni (rst_ni ),
.req_i ( arb_req ), .flush_i('0 ),
.ack_o ( arb_ack ), .rr_i ('0 ),
.vld_o ( ), .req_i (arb_req ),
.idx_o ( arb_idx ) .gnt_o (arb_ack ),
.data_i ('0 ),
.gnt_i (arb_gnt ),
.req_o ( ),
.data_o ( ),
.idx_o (arb_idx )
); );
// request side // request side
...@@ -226,7 +231,7 @@ module wt_axi_adapter #( ...@@ -226,7 +231,7 @@ module wt_axi_adapter #(
end end
end end
fifo_v2 #( fifo_v3 #(
.dtype ( icache_req_t ), .dtype ( icache_req_t ),
.DEPTH ( ReqFifoDepth ) .DEPTH ( ReqFifoDepth )
) i_icache_data_fifo ( ) i_icache_data_fifo (
...@@ -236,15 +241,14 @@ module wt_axi_adapter #( ...@@ -236,15 +241,14 @@ module wt_axi_adapter #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( icache_data_full ), .full_o ( icache_data_full ),
.empty_o ( icache_data_empty ), .empty_o ( icache_data_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( icache_data_i ), .data_i ( icache_data_i ),
.push_i ( icache_data_ack_o ), .push_i ( icache_data_ack_o ),
.data_o ( icache_data ), .data_o ( icache_data ),
.pop_i ( arb_ack[0] ) .pop_i ( arb_ack[0] )
); );
fifo_v2 #( fifo_v3 #(
.dtype ( dcache_req_t ), .dtype ( dcache_req_t ),
.DEPTH ( ReqFifoDepth ) .DEPTH ( ReqFifoDepth )
) i_dcache_data_fifo ( ) i_dcache_data_fifo (
...@@ -254,8 +258,7 @@ module wt_axi_adapter #( ...@@ -254,8 +258,7 @@ module wt_axi_adapter #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( dcache_data_full ), .full_o ( dcache_data_full ),
.empty_o ( dcache_data_empty ), .empty_o ( dcache_data_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( dcache_data_i ), .data_i ( dcache_data_i ),
.push_i ( dcache_data_ack_o ), .push_i ( dcache_data_ack_o ),
.data_o ( dcache_data ), .data_o ( dcache_data ),
...@@ -271,7 +274,7 @@ module wt_axi_adapter #( ...@@ -271,7 +274,7 @@ module wt_axi_adapter #(
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_rd_icache_id ( ) i_rd_icache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -288,7 +291,7 @@ module wt_axi_adapter #( ...@@ -288,7 +291,7 @@ module wt_axi_adapter #(
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_rd_dcache_id ( ) i_rd_dcache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
...@@ -305,7 +308,7 @@ module wt_axi_adapter #( ...@@ -305,7 +308,7 @@ module wt_axi_adapter #(
fifo_v3 #( fifo_v3 #(
.DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ), .DATA_WIDTH ( wt_cache_pkg::CACHE_ID_WIDTH ),
.DEPTH ( MetaFifoDepth ) .DEPTH ( MetaFifoDepth )
) i_wr_dcache_id ( ) i_wr_dcache_id (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
......
src/cache_subsystem/wt_dcache_mem.sv
+ 18
− 12
View file @ 95e099ca
...@@ -135,20 +135,26 @@ module wt_dcache_mem #( ...@@ -135,20 +135,26 @@ module wt_dcache_mem #(
assign rd_req_prio = rd_req_i & rd_prio_i; assign rd_req_prio = rd_req_i & rd_prio_i;
assign rd_req_masked = (|rd_req_prio) ? rd_req_prio : rd_req_i; assign rd_req_masked = (|rd_req_prio) ? rd_req_prio : rd_req_i;
// read port arbiter logic rd_req;
rrarbiter #( rr_arb_tree #(
.NUM_REQ(NumPorts) .NumIn (NumPorts),
) i_rrarbiter ( .DataWidth (1)
.clk_i ( clk_i ), ) i_rr_arb_tree (
.rst_ni ( rst_ni ), .clk_i (clk_i ),
.flush_i( 1'b0 ), .rst_ni (rst_ni ),
.en_i ( ~wr_cl_vld_i ), .flush_i('0 ),
.req_i ( rd_req_masked ), .rr_i ('0 ),
.ack_o ( rd_ack_o ), .req_i (rd_req_masked ),
.vld_o ( rd_acked ), .gnt_o (rd_ack_o ),
.idx_o ( vld_sel_d ) .data_i ('0 ),
.gnt_i (~wr_cl_vld_i ),
.req_o (rd_req ),
.data_o ( ),
.idx_o (vld_sel_d )
); );
assign rd_acked = rd_req & ~wr_cl_vld_i;
always_comb begin : p_bank_req always_comb begin : p_bank_req
vld_we = wr_cl_vld_i; vld_we = wr_cl_vld_i;
bank_req = '0; bank_req = '0;
......
src/cache_subsystem/wt_dcache_wbuffer.sv
+ 52
− 39
View file @ 95e099ca
...@@ -129,6 +129,8 @@ module wt_dcache_wbuffer #( ...@@ -129,6 +129,8 @@ module wt_dcache_wbuffer #(
logic [63:0] debug_paddr [DCACHE_WBUF_DEPTH-1:0]; logic [63:0] debug_paddr [DCACHE_WBUF_DEPTH-1:0];
wbuffer_t wbuffer_check_mux, wbuffer_dirty_mux;
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
// misc // misc
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
...@@ -168,7 +170,7 @@ module wt_dcache_wbuffer #( ...@@ -168,7 +170,7 @@ module wt_dcache_wbuffer #(
); );
// add the offset to the physical base address of this buffer entry // add the offset to the physical base address of this buffer entry
assign miss_paddr_o = {wbuffer_q[dirty_ptr].wtag, bdirty_off}; assign miss_paddr_o = {wbuffer_dirty_mux.wtag, bdirty_off};
assign miss_id_o = tx_id; assign miss_id_o = tx_id;
// is there any dirty word to be transmitted, and is there a free TX slot? // is there any dirty word to be transmitted, and is there a free TX slot?
...@@ -181,7 +183,7 @@ module wt_dcache_wbuffer #( ...@@ -181,7 +183,7 @@ module wt_dcache_wbuffer #(
assign miss_size_o = toSize64(bdirty[dirty_ptr]); assign miss_size_o = toSize64(bdirty[dirty_ptr]);
// replicate transfers shorter than a dword // replicate transfers shorter than a dword
assign miss_wdata_o = repData64(wbuffer_q[dirty_ptr].data, assign miss_wdata_o = repData64(wbuffer_dirty_mux.data,
bdirty_off, bdirty_off,
miss_size_o[1:0]); miss_size_o[1:0]);
...@@ -193,7 +195,7 @@ module wt_dcache_wbuffer #( ...@@ -193,7 +195,7 @@ module wt_dcache_wbuffer #(
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
// TODO: todo: make this fall through if timing permits it // TODO: todo: make this fall through if timing permits it
fifo_v2 #( fifo_v3 #(
.FALL_THROUGH ( 1'b0 ), .FALL_THROUGH ( 1'b0 ),
.DATA_WIDTH ( $clog2(DCACHE_MAX_TX) ), .DATA_WIDTH ( $clog2(DCACHE_MAX_TX) ),
.DEPTH ( DCACHE_MAX_TX ) .DEPTH ( DCACHE_MAX_TX )
...@@ -204,8 +206,7 @@ module wt_dcache_wbuffer #( ...@@ -204,8 +206,7 @@ module wt_dcache_wbuffer #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( ), .full_o ( ),
.empty_o ( rtrn_empty ), .empty_o ( rtrn_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o( ),
.data_i ( miss_rtrn_id_i ), .data_i ( miss_rtrn_id_i ),
.push_i ( miss_rtrn_vld_i ), .push_i ( miss_rtrn_vld_i ),
.data_o ( rtrn_id ), .data_o ( rtrn_id ),
...@@ -243,19 +244,23 @@ module wt_dcache_wbuffer #( ...@@ -243,19 +244,23 @@ module wt_dcache_wbuffer #(
assign free_tx_slots = |(~tx_vld_o); assign free_tx_slots = |(~tx_vld_o);
// get free TX slot // next word to lookup in the cache
rrarbiter #( rr_arb_tree #(
.NUM_REQ ( DCACHE_MAX_TX ), .NumIn (DCACHE_MAX_TX),
.LOCK_IN ( 1 )// lock the decision, once request is asserted .LockIn (1'b1),
.DataWidth (1)
) i_tx_id_rr ( ) i_tx_id_rr (
.clk_i ( clk_i ), .clk_i (clk_i ),
.rst_ni ( rst_ni ), .rst_ni (rst_ni ),
.flush_i ( 1'b0 ), .flush_i('0 ),
.en_i ( dirty_rd_en ), .rr_i ('0 ),
.req_i ( ~tx_vld_o ), .req_i (~tx_vld_o ),
.ack_o ( ), .gnt_o ( ),
.vld_o ( ), .data_i ('0 ),
.idx_o ( tx_id ) .gnt_i (dirty_rd_en ),
.req_o ( ),
.data_o ( ),
.idx_o (tx_id )
); );
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
...@@ -266,7 +271,7 @@ module wt_dcache_wbuffer #( ...@@ -266,7 +271,7 @@ module wt_dcache_wbuffer #(
// trigger TAG readout in cache // trigger TAG readout in cache
assign rd_tag_only_o = 1'b1; assign rd_tag_only_o = 1'b1;
assign rd_paddr = wbuffer_q[check_ptr_d].wtag<<3; assign rd_paddr = wbuffer_check_mux.wtag<<3;
assign rd_req_o = |tocheck; assign rd_req_o = |tocheck;
assign rd_tag_o = rd_tag_q;//delay by one cycle assign rd_tag_o = rd_tag_q;//delay by one cycle
assign rd_idx_o = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH]; assign rd_idx_o = rd_paddr[DCACHE_INDEX_WIDTH-1:DCACHE_OFFSET_WIDTH];
...@@ -341,32 +346,40 @@ module wt_dcache_wbuffer #( ...@@ -341,32 +346,40 @@ module wt_dcache_wbuffer #(
); );
// next dirty word to serve // next dirty word to serve
rrarbiter #( rr_arb_tree #(
.NUM_REQ ( DCACHE_WBUF_DEPTH ), .NumIn ( DCACHE_WBUF_DEPTH ),
.LOCK_IN ( 1 )// lock the decision, once request is asserted .LockIn ( 1'b1 ),
.DataType ( wbuffer_t )
) i_dirty_rr ( ) i_dirty_rr (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), .flush_i( '0 ),
.en_i ( dirty_rd_en ), .rr_i ( '0 ),
.req_i ( dirty ), .req_i ( dirty ),
.ack_o ( ), .gnt_o ( ),
.vld_o ( ), .data_i ( wbuffer_q ),
.idx_o ( dirty_ptr ) .gnt_i ( dirty_rd_en ),
.req_o ( ),
.data_o ( wbuffer_dirty_mux ),
.idx_o ( dirty_ptr )
); );
// next word to lookup in the cache // next word to lookup in the cache
rrarbiter #( rr_arb_tree #(
.NUM_REQ ( DCACHE_WBUF_DEPTH ) .NumIn ( DCACHE_WBUF_DEPTH ),
.DataType ( wbuffer_t )
) i_clean_rr ( ) i_clean_rr (
.clk_i ( clk_i ), .clk_i ( clk_i ),
.rst_ni ( rst_ni ), .rst_ni ( rst_ni ),
.flush_i ( 1'b0 ), .flush_i( '0 ),
.en_i ( check_en_d ), .rr_i ( '0 ),
.req_i ( tocheck ), .req_i ( tocheck ),
.ack_o ( ), .gnt_o ( ),
.vld_o ( ), .data_i ( wbuffer_q ),
.idx_o ( check_ptr_d ) .gnt_i ( check_en_d ),
.req_o ( ),
.data_o ( wbuffer_check_mux ),
.idx_o ( check_ptr_d )
); );
/////////////////////////////////////////////////////// ///////////////////////////////////////////////////////
......
common_cells @ 32dd115a
Compare 34d8ed90...32dd115a
Subproject commit 34d8ed90e03209501fa64da5cb30068846caaeca Subproject commit 32dd115abf114e03a9dda0c5963452c8ec82ed04
src/frontend/frontend.sv
+ 2
− 4
View file @ 95e099ca
...@@ -484,8 +484,7 @@ module frontend #( ...@@ -484,8 +484,7 @@ module frontend #(
); );
end end
fifo_v3 #(
fifo_v2 #(
.DEPTH ( 8 ), .DEPTH ( 8 ),
.dtype ( frontend_fetch_t ) .dtype ( frontend_fetch_t )
) i_fetch_fifo ( ) i_fetch_fifo (
...@@ -495,8 +494,7 @@ module frontend #( ...@@ -495,8 +494,7 @@ module frontend #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( ), .full_o ( ),
.empty_o ( fifo_empty ), .empty_o ( fifo_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( {icache_vaddr_q, icache_data_q, bp_sbe, taken[INSTR_PER_FETCH:1], icache_ex_valid_q} ), .data_i ( {icache_vaddr_q, icache_data_q, bp_sbe, taken[INSTR_PER_FETCH:1], icache_ex_valid_q} ),
.push_i ( fifo_valid ), .push_i ( fifo_valid ),
.data_o ( fetch_entry_o ), .data_o ( fetch_entry_o ),
......
tb/tb_wt_dcache/hdl/tb.sv
+ 2
− 3
View file @ 95e099ca
...@@ -267,7 +267,7 @@ module tb; ...@@ -267,7 +267,7 @@ module tb;
assign fifo_flush[k] = req_ports_i[k].kill_req; assign fifo_flush[k] = req_ports_i[k].kill_req;
assign fifo_pop[k] = req_ports_o[k].data_rvalid; assign fifo_pop[k] = req_ports_o[k].data_rvalid;
fifo_v2 #( fifo_v3 #(
.dtype(resp_fifo_t) .dtype(resp_fifo_t)
) i_resp_fifo ( ) i_resp_fifo (
.clk_i ( clk_i ), .clk_i ( clk_i ),
...@@ -276,8 +276,7 @@ module tb; ...@@ -276,8 +276,7 @@ module tb;
.testmode_i ( '0 ), .testmode_i ( '0 ),
.full_o ( ), .full_o ( ),
.empty_o ( ), .empty_o ( ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( fifo_data_in[k] ), .data_i ( fifo_data_in[k] ),
.push_i ( fifo_push[k] ), .push_i ( fifo_push[k] ),
.data_o ( fifo_data[k] ), .data_o ( fifo_data[k] ),
......
tb/tb_wt_dcache/hdl/tb_mem.sv
+ 4
− 6
View file @ 95e099ca
...@@ -244,7 +244,7 @@ module tb_mem #( ...@@ -244,7 +244,7 @@ module tb_mem #(
end end
end end
fifo_v2 #( fifo_v3 #(
.dtype(dcache_req_t), .dtype(dcache_req_t),
.DEPTH(2) .DEPTH(2)
) i_outfifo ( ) i_outfifo (
...@@ -254,8 +254,7 @@ module tb_mem #( ...@@ -254,8 +254,7 @@ module tb_mem #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( outfifo_full ), .full_o ( outfifo_full ),
.empty_o ( outfifo_empty ), .empty_o ( outfifo_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( mem_data_i ), .data_i ( mem_data_i ),
.push_i ( outfifo_push ), .push_i ( outfifo_push ),
.data_o ( outfifo_data ), .data_o ( outfifo_data ),
...@@ -265,7 +264,7 @@ module tb_mem #( ...@@ -265,7 +264,7 @@ module tb_mem #(
assign outfifo_push = mem_data_req_i & (~outfifo_full); assign outfifo_push = mem_data_req_i & (~outfifo_full);
assign mem_data_ack_o = outfifo_push; assign mem_data_ack_o = outfifo_push;
fifo_v2 #( fifo_v3 #(
.dtype(dcache_rtrn_t), .dtype(dcache_rtrn_t),
.DEPTH(2) .DEPTH(2)
) i_infifo ( ) i_infifo (
...@@ -275,8 +274,7 @@ module tb_mem #( ...@@ -275,8 +274,7 @@ module tb_mem #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( infifo_full ), .full_o ( infifo_full ),
.empty_o ( infifo_empty ), .empty_o ( infifo_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( infifo_data ), .data_i ( infifo_data ),
.push_i ( infifo_push ), .push_i ( infifo_push ),
.data_o ( mem_rtrn_o ), .data_o ( mem_rtrn_o ),
......
tb/tb_wt_dcache/tb.list
+ 0
− 2
View file @ 95e099ca
...@@ -9,11 +9,9 @@ ...@@ -9,11 +9,9 @@
../../src/cache_subsystem/wt_dcache_wbuffer.sv ../../src/cache_subsystem/wt_dcache_wbuffer.sv
../../src/cache_subsystem/wt_dcache.sv ../../src/cache_subsystem/wt_dcache.sv
../../src/common_cells/src/lfsr_8bit.sv ../../src/common_cells/src/lfsr_8bit.sv
../../src/common_cells/src/fifo_v2.sv
../../src/common_cells/src/fifo_v3.sv ../../src/common_cells/src/fifo_v3.sv
../../src/common_cells/src/lzc.sv ../../src/common_cells/src/lzc.sv
../../src/common_cells/src/rr_arb_tree.sv ../../src/common_cells/src/rr_arb_tree.sv
../../src/common_cells/src/rrarbiter.sv
../../src/util/sram.sv ../../src/util/sram.sv
hdl/tb_pkg.sv hdl/tb_pkg.sv
hdl/tb_mem.sv hdl/tb_mem.sv
......
tb/tb_wt_icache/hdl/mem_emul.sv
+ 6
− 9
View file @ 95e099ca
...@@ -181,7 +181,7 @@ module mem_emul #( ...@@ -181,7 +181,7 @@ module mem_emul #(
end end
end end
fifo_v2 #( fifo_v3 #(
.dtype(icache_req_t), .dtype(icache_req_t),
.DEPTH(2) .DEPTH(2)
) i_outfifo ( ) i_outfifo (
...@@ -191,8 +191,7 @@ module mem_emul #( ...@@ -191,8 +191,7 @@ module mem_emul #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( outfifo_full ), .full_o ( outfifo_full ),
.empty_o ( outfifo_empty ), .empty_o ( outfifo_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( mem_data_i ), .data_i ( mem_data_i ),
.push_i ( outfifo_push ), .push_i ( outfifo_push ),
.data_o ( outfifo_data ), .data_o ( outfifo_data ),
...@@ -202,7 +201,7 @@ module mem_emul #( ...@@ -202,7 +201,7 @@ module mem_emul #(
assign outfifo_push = mem_data_req_i & (~outfifo_full); assign outfifo_push = mem_data_req_i & (~outfifo_full);
assign mem_data_ack_o = outfifo_push; assign mem_data_ack_o = outfifo_push;
fifo_v2 #( fifo_v3 #(
.dtype(icache_rtrn_t), .dtype(icache_rtrn_t),
.DEPTH(2) .DEPTH(2)
) i_infifo ( ) i_infifo (
...@@ -212,8 +211,7 @@ module mem_emul #( ...@@ -212,8 +211,7 @@ module mem_emul #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( infifo_full ), .full_o ( infifo_full ),
.empty_o ( infifo_empty ), .empty_o ( infifo_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( infifo_data ), .data_i ( infifo_data ),
.push_i ( infifo_push ), .push_i ( infifo_push ),
.data_o ( mem_rtrn_o ), .data_o ( mem_rtrn_o ),
...@@ -224,7 +222,7 @@ module mem_emul #( ...@@ -224,7 +222,7 @@ module mem_emul #(
assign mem_rtrn_vld_o = infifo_pop; assign mem_rtrn_vld_o = infifo_pop;
// this is to readout the expected responses // this is to readout the expected responses
fifo_v2 #( fifo_v3 #(
.DATA_WIDTH(64), .DATA_WIDTH(64),
.DEPTH(3) .DEPTH(3)
) i_stimuli_fifo ( ) i_stimuli_fifo (
...@@ -234,8 +232,7 @@ module mem_emul #( ...@@ -234,8 +232,7 @@ module mem_emul #(
.testmode_i ( 1'b0 ), .testmode_i ( 1'b0 ),
.full_o ( stim_full_o ), .full_o ( stim_full_o ),
.empty_o ( exp_empty ), .empty_o ( exp_empty ),
.alm_full_o ( ), .usage_o ( ),
.alm_empty_o ( ),
.data_i ( stim_vaddr_i ), .data_i ( stim_vaddr_i ),
.push_i ( stim_push_i ), .push_i ( stim_push_i ),
.data_o ( stim_addr ), .data_o ( stim_addr ),
......
tb/tb_wt_icache/tb.list
+ 0
− 1
View file @ 95e099ca
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
../../src/fpga-support/rtl/SyncSpRamBeNx64.sv ../../src/fpga-support/rtl/SyncSpRamBeNx64.sv
../../src/cache_subsystem/wt_icache.sv ../../src/cache_subsystem/wt_icache.sv
../../src/common_cells/src/lfsr_8bit.sv ../../src/common_cells/src/lfsr_8bit.sv
../../src/common_cells/src/fifo_v2.sv
../../src/common_cells/src/fifo_v3.sv ../../src/common_cells/src/fifo_v3.sv
../../src/common_cells/src/lzc.sv ../../src/common_cells/src/lzc.sv
../../src/util/sram.sv ../../src/util/sram.sv
......
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