Commits · 278737c74b92b458ab6fd7710658ceeacd97b885 · MINOTAuR / printemps · GitLab

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Oct 18, 2024
- README updated, constraints vcu118 added · 278737c7
  Pascal SAINRAT authored 8 months ago
  
  278737c7
- sythesis works for vcu118 and coremarks run · 4cc65bea
  tcarle authored 8 months ago
  
  4cc65bea
Nov 16, 2023
- fpga: port Ariane to the Ultrascale ZCU104 · edca53de
  Alban Gruin authored 2 years ago
  edca53de
Jan 05, 2021
- updating repo to support ps7 ddr memory · 29aac770
  sjthales authored 4 years ago
  
  29aac770
Dec 08, 2020
- updating to into account serial number of HS2 cable · 7794673d
  sjthales authored 4 years ago
  
  7794673d
- correcting name of script for hs2 cable · 00871ce3
  sjthales authored 4 years ago
  
  00871ce3
Dec 07, 2020
- updating README, top module,top module testbench on Zybo z7-20 board · 3e76ea25
  sjthales authored 4 years ago
  
  3e76ea25
Dec 04, 2020
- updating README to implement CV32A6 on Zybo z7-20 board · 247d11ef
  sjthales authored 4 years ago
  
  247d11ef
- update to implement cv32a6 on zybo z7-20 board · 64bda94d
  sjthales authored 4 years ago
  
  64bda94d
Oct 09, 2020
- modification student contest · acf7dc6a
  sjthales authored 4 years ago
  
  acf7dc6a
Sep 08, 2020
- cva6: Fix signals on the FPGA model (#513) · 3663eebd
  Ruige Lee authored 4 years ago
  Unverified
  
  3663eebd
Aug 27, 2020
- Revert "Add FPGA Optimized Register File Version" · eef5ff6d
  Florian Zaruba authored 4 years ago
  Unverified
  
  eef5ff6d
Aug 24, 2020
- Add FPGA Optimized Register File Version · c69ebadc
  ganoam authored 4 years ago
  c69ebadc
Feb 04, 2020
- dts: Fix FPGA timebase to 25MHz (#374) · 4b410a88
  Stefan authored 5 years ago
  Unverified
  
  4b410a88
Jan 22, 2020
- fpga/run.tcl: Fix empty match rule · ad70ce1f
  Jimmy Situ authored 5 years ago
  
  Unverified
  
  ad70ce1f
- ariane_soc: Add APB timer peripheral (#361) · 08c71a22
  Nils Wistoff authored 5 years ago
  
  08c71a22
Dec 03, 2019
- ariane.cfg: catch unavailable address translation option · cb74091a
  Nils Wistoff authored 5 years ago
  
  cb74091a
- ariane.cfg: enable address translation per default when debugging · b04066a2
  Nils Wistoff authored 5 years ago
  
  b04066a2
Oct 23, 2019
- Fixup `trst` in the ariane_xilinx.sv portlist (#336) · b4561731
  jmason827 authored 5 years ago
  b4561731
Oct 11, 2019
- fpga: Add VC707 compatibility (#335) · 955bbdb8
  jmason827 authored 5 years ago
  955bbdb8
Oct 09, 2019
- fpga: Add support for Xilinx Kintex-7 FPGA KC705 Evaluation Kit (#262) · a45a2360
  Stefan authored 5 years ago
  a45a2360
Oct 08, 2019
- fpga: Fix empty match file in flow (#334) · 17f43042
  Jimmy Situ authored 5 years ago
  
  17f43042
Jun 04, 2019
- Fix run.tcl (moved include path declaration to the beginning) · 7b305dd6
  Michael Schaffner authored 6 years ago
  
  7b305dd6
- Bump axi submodule to v0.7 and fix include path for registers.svh in run.tcl · c06f6a2a
  Michael Schaffner authored 6 years ago
  
  c06f6a2a
- Fix include path for registers.svh in run.tcl · 39e4ebce
  Michael Schaffner authored 6 years ago
  
  39e4ebce
- Remove duplicated interface aliases · 957ba3ad
  Jonathan Richard Robert Kimmitt authored 6 years ago
  
  957ba3ad
- fpga: Remove `default_nettype` for Vivado 2018.3 · 879b1c2c
  Florian Zaruba authored 6 years ago
  
  879b1c2c
- Adds cacheable region rules to the configuration script, modify instruction... · 63021b9d
  Michael Schaffner authored 6 years ago
  63021b9d
- openocd: Add multi-hart config · 078c5c16
  Michael Schaffner authored 6 years ago
  
  078c5c16
- debug: Bump `dm` version · c340a683
  Michael Schaffner authored 6 years ago
  c340a683
- rv_plic: Add lowrisc PLIC · 5bf0d925
  Florian Zaruba authored 6 years ago
  5bf0d925
Mar 18, 2019
- Clean-up naming to distinguish OP from GP Ariane (#193) · ad223cfd
  Florian Zaruba authored 6 years ago
  ad223cfd
- Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) · a5f3184a
  Florian Zaruba authored 6 years ago
  a5f3184a
- Fix AMO problem in verilator · a4e49fc8
  Florian Zaruba authored 6 years ago
  
  a4e49fc8
- Maturity fixes and AXI extensions for write-through cache system (#188) · 07df1426
  msfschaffner authored 6 years ago
  07df1426
- Add Exclusive Adapter (#187) · 84330030
  Florian Zaruba authored 6 years ago
  84330030
- Add System Verilog FPU (#163) · b1bdc0c0
  Florian Zaruba authored 6 years ago
  b1bdc0c0
Feb 15, 2019
- Adjust Memory size to Genesys2 maximum (1GByte) (#177) · 3ca3a28a
  jrrk authored 6 years ago
  
  3ca3a28a
Feb 06, 2019
- Correct mdio_oe naming, streamline to allow 1GHz capability · 40bc4de9
  Jonathan Richard Robert Kimmitt authored 6 years ago
  
  40bc4de9
Feb 05, 2019
- Bugfix in FPGA bootrom · a43ebc15
  Moritz Schneider authored 6 years ago
  Unverified
  
  a43ebc15