Commits · sicariane · MINOTAuR / MINOTAuR · GitLab

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Jan 05, 2021
- updating repo to support ps7 ddr memory · 29aac770
  sjthales authored 4 years ago
  
  29aac770
Dec 08, 2020
- Update Makefile · 4b0b5c08
  sébastien jacq authored 4 years ago
  
  Unverified
  
  4b0b5c08
- updating to into account serial number of HS2 cable · 7794673d
  sjthales authored 4 years ago
  
  7794673d
Dec 04, 2020
- update to implement cv32a6 on zybo z7-20 board · 64bda94d
  sjthales authored 4 years ago
  
  64bda94d
Oct 09, 2020
- modification student contest · acf7dc6a
  sjthales authored 4 years ago
  
  acf7dc6a
Aug 27, 2020
- Revert "Add FPGA Optimized Register File Version" · eef5ff6d
  Florian Zaruba authored 4 years ago
  Unverified
  
  eef5ff6d
Aug 25, 2020
- ci: Consolidate tests · 8de6e352
  Florian Zaruba authored 4 years ago
  8de6e352
- verilator: Add memory preloading · 3a13ae03
  Florian Zaruba authored 4 years ago
  3a13ae03
Aug 24, 2020
- Add FPGA Optimized Register File Version · c69ebadc
  ganoam authored 4 years ago
  c69ebadc
Jul 14, 2020
- modelsim: fix simulation flow · c30e2618
  Nils Wistoff authored 4 years ago
  
  c30e2618
- pmp: Add pmps and riscv definitions · 78361954
  Florian Zaruba authored 5 years ago
  78361954
- pmp: Wire pmp registers to lsu · d210a143
  Moritz Schneider authored 5 years ago
  
  d210a143
Jun 16, 2020
- verification: Add co-simulation with dromajo (#445) · 2d814452
  Nursultan Kabylkas authored 5 years ago
  Unverified
  
  2d814452
May 15, 2020
- Makefile: Fix `verilator` variable (#427) · 79d4be75
  Wilson Snyder authored 5 years ago
  Unverified
  
  79d4be75
Feb 04, 2020
- ariane-soc: Enable the mock-uart on Verilator · 55201929
  Edgar E. Iglesias authored 5 years ago
  55201929
Jan 22, 2020
- ariane_soc: Add APB timer peripheral (#361) · 08c71a22
  Nils Wistoff authored 5 years ago
  
  08c71a22
Oct 11, 2019
- fpga: Add VC707 compatibility (#335) · 955bbdb8
  jmason827 authored 5 years ago
  955bbdb8
Oct 09, 2019
- fpga: Add support for Xilinx Kintex-7 FPGA KC705 Evaluation Kit (#262) · a45a2360
  Stefan authored 5 years ago
  a45a2360
Jul 14, 2019
- wt_cache: Enable exp back-off for LR/SC (#280) · 6766c736
  Fei Gao authored 5 years ago
  6766c736
Jul 12, 2019
- ci: Add mul and fp tests (#278) · 9f461ad5
  Stefan Mach authored 5 years ago
  9f461ad5
Jul 10, 2019
- fpu: Bump to fix divsqrt freezing bug (#277) · 68a11c30
  Stefan Mach authored 5 years ago
  68a11c30
Jun 04, 2019
- Bump FPU, DM and common cells · 416aec89
  Michael Schaffner authored 6 years ago
  
  416aec89
- travis: Split into smaller travis tests · 47fe4d35
  zachzzc authored 6 years ago
  
  47fe4d35
- testHarness: Fix the multi-thread library dependency error · 62327627
  zachzzc authored 6 years ago
  
  62327627
- fpu: Bump submodule (#232) · c02597c2
  msfschaffner authored 6 years ago
  
  c02597c2
- frontend: Clean-up instruction frontend · 830540b7
  Florian Zaruba authored 6 years ago
  830540b7
- common_cells: Bump and remove deprecated modules · 95e099ca
  Michael Schaffner authored 6 years ago
  
  95e099ca
- fpu: Add distributed pipe regs to ease FPGA timing · d30369da
  Michael Schaffner authored 6 years ago
  
  d30369da
- Adds cacheable region rules to the configuration script, modify instruction... · 63021b9d
  Michael Schaffner authored 6 years ago
  63021b9d
- testharness: Remove spurious warnings in Verilator · 6eeb0eb1
  Michael Schaffner authored 6 years ago
  6eeb0eb1
- Bump common cells to v1.12 · 42412b96
  Michael Schaffner authored 6 years ago
  
  42412b96
- rv_plic: Add lowrisc PLIC · 5bf0d925
  Florian Zaruba authored 6 years ago
  5bf0d925
Mar 18, 2019
- Clean-up naming to distinguish OP from GP Ariane (#193) · ad223cfd
  Florian Zaruba authored 6 years ago
  ad223cfd
- Improve Tandem Simulation, switch-able caches and fix a cache-bug (#192) · a5f3184a
  Florian Zaruba authored 6 years ago
  a5f3184a
- Maturity fixes and AXI extensions for write-through cache system (#188) · 07df1426
  msfschaffner authored 6 years ago
  07df1426
- Add Exclusive Adapter (#187) · 84330030
  Florian Zaruba authored 6 years ago
  84330030
- Add System Verilog FPU (#163) · b1bdc0c0
  Florian Zaruba authored 6 years ago
  b1bdc0c0
Jan 29, 2019
- Update Makefile with path to ethernet submodule Verilog files · 4a62b8c2
  Jonathan Richard Robert Kimmitt authored 6 years ago
  
  4a62b8c2
Jan 15, 2019
- Fix library path also for Modelsim · f4ec843b
  Florian Zaruba authored 6 years ago
  
  Unverified
  
  f4ec843b
Nov 29, 2018
- Change default include path · e82e678e
  Florian Zaruba authored 6 years ago
  
  Unverified
  
  e82e678e